CEO Interview with Dr. Naveen Verma of EnCharge AINaveen Verma, Ph.D., is the CEO and Co-founder…Read More
WEBINAR: Edge AI Optimization: How to Design Future-Proof Architectures for Next-Gen Intelligent DevicesEdge AI is rapidly transforming how intelligent solutions…Read More
Assertion based verification is a very productive way to catch bugs, however assertions are hard enough to write that assertion-based coverage is not as extensive as it could be. Is there a way to simplify developing assertions to aid in increasing that coverage? Paul Cunningham (Senior VP/GM, Verification at Cadence), Raúl … Read More
Dan is joined by Dan Kochpatcharin, Dan joined TSMC in 2007. Prior to his current role heading up the Design Infrastructure Management Division, Dan led the Japan customer strategy team, the technical marketing and support team for the EMEA region in Amsterdam and was a part of the team leading the formation of the TSMC Open Innovation… Read More
As a follow up from my #60DAC visit with Simon Rance of Keysight I was invited to their recent webinar, Unveiling the Secrets to Proper Version Control, Seamless Data and Tool Integration, and Effective Collaboration. Karim Khalfan, Director of Solutions Engineering, Data & IP Management was the webinar presenter.
Modern… Read More
Artificial Intelligence is now the primary driver of leading edge semiconductor technology and that means performance is at a premium and time to market will be measured in billions of dollars of revenue. Emulation and Prototyping have never been more important and we are seeing some amazing technology breakthroughs including… Read More
In the realm of digital systems, clocks play a crucial role in synchronizing various components and ensuring smooth flow of logic propagation. However, the accuracy of clocks can be significantly affected by power supply induced jitter. Jitter refers to the deviation in the timing of clock signals with PDN noise compared to ideal… Read More
Tis the season for transformer-centric articles apparently – this is my third within a month. Clearly this is a domain with both great opportunities and challenges: extending large language model (LLM) potential to new edge products and revenue opportunities, with unbounded applications and volumes yet challenges in meeting… Read More
Advanced process nodes create challenges for EDA both in handling ever larger designs and increasing design process complexity.
Shift-left design methodologies for design cycle time compression are one response to this. And this has also forced some rethinking about how to build and optimize design tools and flows.
SemiWiki… Read More
SoC designs use many levels of design abstraction during their journey from ideation to implementation, and now it’s possible to perform power analysis quite early in the design process. I had a call with William Ruby, Director of Porduct Marketing – Synopsys Low Power Solution to hear what they’ve engineered… Read More
In the age of rapid technological innovation, hyperscale datacenters are evolving at a breakneck pace. With the continued advancements in CPUs, GPUs, accelerators, and switches, faster data transfers are now paramount. At the forefront of this advancement is PCI Express (PCIe®), which has become the de-facto standard of interconnect… Read More
TSMC originally brought the pure-play foundry business to the United States in 1996 through a joint venture with customers Altera, Analog Devices, ISSI, and private investors (no government money). Altera is now part of Intel but ADI is still a top TSMC customer and enthusiastic supporter. I have seen the ADI CEO Vincent Roche … Read More
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