How Samtec Blazes a Trail to 224/448 Gbps at DesignCon 26I recently covered what Samtec was doing at…Read More
Available Is Not In Control: Balancing Output, Quality, and Risk in High-Volume FabsA deposition chamber drops out of production at…Read More
AION Silicon: Architecting Smarter SoCs with RISC-V: Balancing Performance, Flexibility, and Risk Architecting Smarter SoCs with…Read More
AI-native Virtual Chiplet Eco-systems: Shift Left, Shift Up, and Shift Out to accelerate Chiplet adoptionSystems-in-package (SIPs) with 2.5D and 3D heterogenous integration,…Read More
The Yield Partnership: Intel and PDF Solutions Tackle Advanced NodesOne of the most difficult things to do…Read More
The GlobalFoundries DRC+ platform is one of the most innovative DFM technologies and was well represented at #48DAC. In case you missed it, here is a reprint of a DRC+ overview from GFI just prior to #48DAC:
DRC (Design Rule Constraints) are the fundamental principles in constraining VLSI (Very Large Scale Integration) circuit… Read More
Intro
I met with CK Lee, founder of Cyber EDA at his booth on Monday evening in San Diego. Last year I learned about their new SPICE circuit simulator named PCSIM, this year the new product is called ADDS-Debugger.
Notes
2010 – Announced a debugger
2011 ADDS Debugger – trace at the transistor level your design
– Signal tracing… Read More
Intro
John and Ralph from Magma gave me an update on QuickCap at DAC on Monday afternoon in their demo suite.
Notes
John Schritz – Sr AE
Ralph Iverson, Ph. D. (wrote QuickCap)
John Schritz
– Digital Signoff, extraction
– QCP: 2.5D RC for full ASIC designs
– QuickCAP NX: 3D field solver
– QCP:
Demo – 1.5 million… Read More
Hany El Hak – Product Marketing Manager
Frederik Iverson – AE
Scott Wetch – HSPICE Architect
HSPICE – 5 years ago convergence was not so good, while 95% of analog circuits today converge out of the box, no options are required.
Synopsys AMS Portfolio – wide range of tools
– Custom Designer: IC schematic and layout tools
–… Read More
After lunch on Monday I met with John Heinlin, Ph.D. – VP Marketing of Physical IP Division
Back in the day I knew the founders of Artisan (VLSI Libraries) when we worked together at Silicon Compilers (Mark Templeton, John Malecki, Scott Becker).
Q: Do you favor any EDA tools for creating your IP?
A: No, we don’t really endorse a specific… Read More
Lunch time Monday at DAC and I learned about what’s new at the IPL Alliance in 2011.
IPL Sponsors: Magma, Mentor Graphics, Springsoft, Accelicon, Ciranova, Synopsys, TSMC, TowerJazz, Jedat, Tanner EDA
Two major projects:
1) iPDKS
2) Analog Constraints… Read More
At DAC I spent time in the Magma FineSIM demo suite on Monday morning.
Greg Curtis – Product Director, Custom Design Business Unit
– Talus for Digital Design
– FineSim does: SPICE, FastSPICE, Characterization
– Flows Demoed at DAC: High Performance Core, SOC, ASIC/ASSP, AMS, Memory
– What’s New in FineSim?o… Read More
I met with Bala Vishwanath, CMO at Nimbic on Monday morning. They had just announced a $6.9M round of venture capital which is something that you rarely hear about in EDA these days, especially during a slow economic recovery.
Intro
Physware – served the package and board markets, co-design challenges (can add IC noise sources).… Read More
Everybody knows that digital designers run on pizza and soda, what one might describe as poor food and weak drinks. At DAC in San Diego I discovered a restaurant that gave away the secret to analog design. And you thought it was a good layout editor and a good circuit simulator. But it turns out that the secret to analog is good food and… Read More
Introduction
Monday morning at DAC I attended the breakfast presentation from Magma, ARM and GLOBALFOUNDRIES. The 28nm node is ready for business using Magma tools and ARM libraries.
During breakfast I met Karim Arabi, Ph.D. from QualComm. He’s a senior director of engineering in San Diego and wanted to learn more about… Read More
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Intel 18A vs Intel 18A-P: What Is the Difference and Why Does It Matter?