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TSMC Unveils Details of 5nm CMOS Production Technology Platform Featuring EUV and High Mobility Channel FinFETs at IEDM2019

TSMC Unveils Details of 5nm CMOS Production Technology Platform Featuring EUV and High Mobility Channel FinFETs at IEDM2019
by Don Draper on 02-05-2020 at 10:00 am

Diagram of BEOL metallization comparing EUV vs. immersion photolithography

Back in April, 2019, TSMC announced that they were introducing their 5 nm technology in risk production and now at IEDM 2019 they brought forth a detailed description of the process which has passed 1000 hour HTOL and will be in high volume production in 1H 2020.  This 5nm technology is a full node scaling from 7nm using smart scaling… Read More


Verification, RISC-V and Extensibility

Verification, RISC-V and Extensibility
by Bernard Murphy on 02-05-2020 at 6:00 am

RISC-V

RISC-V is obviously making progress. Independent of licensee signups and new technical offerings, the simple fact that Arm is responding – in fundamental changes to their licensing model and in allowing custom user extensions to the instruction set – is proof enough that they see a real competitive threat from RISC-V.

Which all… Read More


Signal Channel Design and Simulation for Silicon Interposer Packaging on High-Speed SerDes

Signal Channel Design and Simulation for Silicon Interposer Packaging on High-Speed SerDes
by Mike Gianfagna on 02-04-2020 at 10:00 am

Picture2

This year is the 25th anniversary for DesignCon.  The show has changed a lot over the years. Today, it’s a vibrant showcase of all aspects of advanced product design – from ICs to boards to systems. The show floor reflects the diverse ecosystem. If you missed it this year, definitely plan to go next year.

The DesignCon technical program… Read More


Intel vs AMD Q4 2019 Conference Calls

Intel vs AMD Q4 2019 Conference Calls
by Daniel Nenni on 02-04-2020 at 6:00 am

Intel 10nm Roadmap

Now that the dust has settled and I’m out of cronovirus quarantine let’s talk about the Intel and AMD conference calls. Unfortunately, the Intel and AMD marketing teams are still outpacing engineering so it is difficult to write something serious but I will do my best.

Spoiler Alert: Both CEOs disappoint.

First an Intel 10nm update:… Read More


DVCon Is a Must Attend Event for Design and Verification Engineers

DVCon Is a Must Attend Event for Design and Verification Engineers
by Daniel Payne on 02-03-2020 at 10:00 am

dvcon 2020

Learning is a never-ending process for design and verification engineers, so outside of reading SemiWiki you likely want to attend at least a few events per year to keep updated, learn something new, attend a workshop, or even present something that has made your IC project work much better than before. Sure, DAC is always a great… Read More


Logic and Memory Make for a Recovery

Logic and Memory Make for a Recovery
by Robert Maire on 02-03-2020 at 6:00 am

Lam Research 2020
  • LAM- “Logic And Memory” make for a recovery-NAND (Samsung) & Logic (TSMC) + China
  • Great Q4 Results & Q1 guide as memory restarts
  • Logic strength continues-China is crucial to growth
  • 2019 better than expected- 2020 WFE up about 5-8%

Lam reports nice finish to 2019 and start of 2020
The company reported revenues… Read More


The Tech Week that was January 27-31 2020

The Tech Week that was January 27-31 2020
by Mark Dyson on 02-02-2020 at 6:00 am

Semiconductor Weekly Summary 1

This week the Coronavirus has been escalated to a Global Health Emergency status by the WHO, China extended the Chinese New Year shutdown to 9th February and many companies have implemented a travel ban on business travel to/from China or Asia as well as implementing other business continuity procedures. The last crisis in 2003Read More


Privacy is Different in Cars

Privacy is Different in Cars
by Roger C. Lanctot on 01-31-2020 at 6:00 am

Privacy is Different in Cars

The New Yorks Times’ “The Privacy Project” highlights all that is terrifying about our surveillance economy. We blithely throw away our privacy for the privilege of freely accessing mountains of information about the things we want to buy, the celebrities and teams we follow or support, or to get directions

Read More

Bringing Hierarchy to DFT

Bringing Hierarchy to DFT
by Tom Simon on 01-30-2020 at 6:00 am

Tessent Hierarchical Flow

Hierarchy is nearly universally used in the SoC design process to help manage complexity. Dealing with flat logical or physical designs proved unworkable decades ago. However, there were a few places in the flow where flat tools continued to be used. Mentor lead the pack in the years around 1999 in helping the industry move from … Read More


WEBINAR: Prototyping With Intel’s New 80M Gate FPGA

WEBINAR: Prototyping With Intel’s New 80M Gate FPGA
by Daniel Nenni on 01-29-2020 at 10:00 am

The next generation FPGAs have been announced, and they are BIG!  Intel is shipping its Stratix 10 GX 10M FPGA, and Xilinx has announced its VU19P FPGA for general availability in the Fall of next year.  The former is expected to support about 80M ASIC gates, and the latter about 50M ASIC gates.  And, to bring this mind-boggling gate… Read More