Verification Engineer

Job Description

• Good understanding of Verilog, SV and UVM concept.
• Hands on exp in writing UVM based testbench.
• Good debugging skills.
• Knowledge of AHB/AXI protocol.
• Worked on Assertion based verification.
• Should have knowledge of FIFO and command/response based verification
• Knowledge of cryptography/random number generator and security concept is advantage.
• Formal or jasper understanding.
• Worked on Verdi tool for debugging.
• Should have knowledge of Code and Functional coverage.
• Must have exp in handling some project and team.
• Knowledge of processor and silicon bringup.

Skills

• AHB
• AXI
• jasper
• UVM
• Verilog