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Verification Engineer

Verification Engineer
by Admin on 05-03-2023 at 11:40 am

Job Description

  • Good understanding of Verilog, SV and UVM concept.
  • Hands on exp in writing UVM based testbench.
  • Good debugging skills.
  • Knowledge of AHB/AXI protocol.
  • Worked on Assertion based verification.
  • Should have knowledge of FIFO and command/response based verification
  • Knowledge of cryptography/random number generator and security concept is advantage.
  • Formal or jasper understanding.
  • Worked on Verdi tool for debugging.
  • Should have knowledge of Code and Functional coverage.
  • Must have exp in handling some project and team.
  • Knowledge of processor and silicon bringup.


  • AHB
  • AXI
  • jasper
  • UVM
  • Verilog
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