Senior Staff Hardware Verification Engineer

Our technology helps the world’s most visionary companies—from startups to Fortune 500 leaders—build smarter, faster semiconductors, specifically SoCs and chiplets. From the car you drive to the AI in the cloud, Arteris connects the innovative technology that shapes tomorrow.

Your Role as a Senior Hardware Verification Engineer at Arteris

Join our engineering team and contribute to the verification of cutting-edge hardware solutions in the semiconductor domain, particularly Arteris’ highly configurable Network-on-Chip (NoC) IP.

In this role, you will be responsible for defining, implementing, and executing robust verification strategies to ensure the quality, reliability, and performance of our hardware IP. You will work closely with design, architecture, and validation teams to achieve comprehensive verification coverage.

Key Responsibilities

• Define, document, develop, and execute RTL verification environments and test/coverage plans for highly parameterized IP
• Develop verification testbenches and infrastructures in Python and C++, compatible with major RTL simulators (Cadence, Synopsys, etc.)
• Implement and maintain verification components such as BFMs, monitors, and checkers
• Maintain and improve verification flows, coverage metrics, and automation levels
• Collaborate closely with RTL design and architecture teams to identify and resolve verification issues

What You Bring 

• More than 5 years of industry experience as a hardware verification engineer
• Strong understanding of RTL hardware design
• Proficiency in verification languages and environments: VHDL, Verilog, SystemVerilog, SystemC, C++, Python
• Solid experience with verification methodologies and infrastructures (UVM, VIPs, testbenches, EDA tools)
• Shell scripting skills
• Good understanding of hardware communication protocols (AMBA, OCP, or similar)
• Strong analytical and problem-solving skills with high attention to detail
• Proven ability to work effectively in a team
• Good written and spoken communication skills in English (French is a plus)
• Self-motivated, rigorous, curious, and quality-driven

Preferred Qualifications

• Experience with formal verification methodologies
• Knowledge of interconnect technologies (NoC, interconnect IP)
• Background in EDA and SoC design flows

Education Requirements 

• PhD or Master’s degree in Electrical Engineering, Computer Science, Microelectronics, or a related field, or equivalent professional experience

Compensation 

Estimated Base Salary: €45,000 to €55,000 annually.

Your base salary will be determined based on your location, experience, and internal pay equity for similar roles.