- Develop PVL DRC, LVS, LPE rule decks for worldwide foundries.
- Manage onsite technical qualification so that both PVL decks and tool are qualified by foundries for official support.
- Work closely with early adoption customers to track and resolve product issues
- Provide communication channel for R&D to capture customer needs and requirement spec.
- Work closely with R&D to develop and improve Pegasus to be leading edge Physical Verification tool
- B.S. in Electrical Engineering (EE), Computer Science (CS), or related area (or equivalent) and 3 – 5 years of experience with Physical Verification tool support/development OR
- M.S. in EE or CS, or related area (or equivalent) and 1 – 3 years of experience with Physical Verification tool support/development
- Profound knowledge with Foundry Design Rules and semiconductor fabrication process
- Be able to develop PVL rule deck for worldwide foundries with good quality and performance meeting their schedules and qualification requirements.
- Excellent Script programming skill with TCL and PERL is required
- Good communication skills in English
- Software development, Cadence SKILL programming experience preferred, while IC design, CAD support experience is a plus
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