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ISP ASIC Design Engineer

ISP ASIC Design Engineer
by Admin on 03-15-2023 at 12:29 pm


Design micro-architecture for image processing algorithms, spec definition, Block and top level RTL implementation, optimization and verification, Design flow and FPGA validation.


  • Work experience and rank are not limited, master degree and above with related major, programming skills in Verilog HDL.
  • Knowledge of Image or video processing.
  • Experience of ASIC design (including specification, micro-architecture, and RTL implementation).
  • Be familiar with design flow (Synthesis, Lint, CDC, DFT, and etc.).
  • Experience of Image processor design, such as 3D noise reduction, HDR, white balance, image enhancer will be a plus.
  • Highly motivated and skillful at solving difficult technical problems.
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