800x100 static WP 3 (2)

DDR PHY RTL Design Engineer

DDR PHY RTL Design Engineer
by Admin on 02-27-2020 at 1:20 pm

Website Cadence

Required skills

  • BSEE or equivalent and a minimum of 3 years of RTL design experience.
  • Requires a strong background in design specification, design, and implementation, including  Verilog RTL coding, synthesis and STA experience.
  • Previous experience designing configurable IP is a strong plus.
  • Strong command of Verilog/System Verilog language
  • Strong command of simulation, lint, synthesis, STA, formal verification, functional coverage, design for test, and design methodologies
  • Ability to handle multiple projects/tasks successfully
  • Good oral and written communication skills
  • Familiar with TCL, Python.

Desired skills

  • Knowledge of DDR/GDDR DRAM protocol
  • Experience designing or integrating IP
  • Experience in high speed and low power digital design using advanced deep micron process.
  • Experience with highly configurable designs
Apply for job

To view the job application please visit cadence.wd1.myworkdayjobs.com.

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