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ASIC/Layout Design Engr, II

ASIC/Layout Design Engr, II
by Admin on 03-18-2020 at 11:50 pm

Website Synopsys

Job Description and Requirements

– Knowledge of CMOS processes and issues in deep submicron process technologies.

– CMOS circuit design and layout design concept,  good understanding and experience on Standard cell layout in 7nm and 5nm

– Familiarity with ASIC design flow.

– Good written and verbal communication skills in interactions with internal development teams.

Apply for job

To view the job application please visit sjobs.brassring.com.

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