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ASIC Digital Design Engr, Sr I

ASIC Digital Design Engr, Sr I
by Admin on 09-26-2022 at 1:45 pm

Website Synopsys

The candidate will be part of the R&D in Solutions Group at our Bangalore Design Center, India.

The position offers learning and growth opportunities. This is a Technical Person Contributor role and offers challenges to work in a multi-site environment on technically challenging IP Cores in a role that will  include  IP Verification using latest Verification methodology  Flows .

Job Description

  • The candidate will be part of the DesignWare IP Verification R&D team at Synopsys.
  • The candidate will be expected to specify, design/architect and implement state-of-the-art Verification environments for the DesignWare family of synthesizable cores and perform Verification tasks for the IP cores.
  • The candidate will work closely with RTL designers and be part of a global team of skilled Verification Engineers.
  • Will be working on the next generation connectivity protocols for commercial, Enterprise and Automotive applications
  • Job role will have a combination of Test planning, Test environment coding both at unit level and system level, Test case coding and debugging, FC coding and exploration and meeting quality metric goals and regression management.

Requirements:

  • Must have BSEE in EE with 5+ years of relevant experience or MSEE with 4+ years of relevant experience in the following areas:
  • Must have experience in developing HVL (System Verilog) based test environments, developing and implementing test plans, implementing and extracting verification metrics such as functional coverage.
  • Must have excellent HVL coding skills for Verification and be hands-on with one or more Industry standard simulators such as VCS, NC, MTI used in Verification and waveform based debugging tools.
  • Exposure to verification methodologies such as VMM/OVM/UVM/ is required.
  • Understanding of one or more of protocols: AMBA (AMBA2, AXI), SD/eMMC, MIPI-I3C/UFS/Unipro, Ethernet,  DDR, PCIe, USB
  • Experience with verification of  Scatter Gather DMA. Host controller interface is a significant plus.
  • Familiarity with HDLs such as Verilog  and scripting languages such as Perl, TCL, Python is highly desired.
  • Exposure to IP design and verification processes including VIP development is an added advantage.
  • There will be focus on functional coverage guided methodology. So the corresponding mindset is a must.
  • It is essential that the person has good written and oral communication skills and is able to demonstrate good exploration, debug and problem solving skills and show high levels of initiative.
  • This position requires prior industry experience and  is not open for college fresh grads.

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

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To view the job application please visit sjobs.brassring.com.

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