ASIC Digital Design Engr, II

Job Description and Requirements

We are looking for highly motivated and innovative digital designer with strong theoretical and practical background in high-speed serializer and data recovery circuits. Working as both an individual and a team member, the candidate will be involved in designing and maintaining current and next generation USB, PCI Express, SATA, and Ethernet PHY products. The position offers excellent opportunity to work with an expert team of digital and mixed signal designers responsible for delivering high-end mixed-signal designs from specification development to performing functional and performance tests on the test-chips.

Job Responsibilities:

• Architecture design and test-plans for high-speed digital circuits.
• RTL coding, modeling of analog blocks, and writing complex system-level test-benches in Verilog.
• Defining synthesis constraints and resolving STA issues and gate-level simulations.
• Enhancing and maintaining Serdes cores.
• Interacting with customer support and back-end design teams.
• Mentoring junior engineers and defining efficient design and verification methodologies.

Job Requirements:

• BSEE/MSEE plus at least 3 years of digital design and verification experience in the industry.
• Good experience in writing complex test-cases including constrained random tests.
• Must be familiar with Verilog and VCS. Good knowledge of back-end synthesis tools DC/PT is required.
• Must have thorough knowledge of digital design methodologies, scan insertion, ATE through JTAG, and synthesis constraints.
• Scripting experience in Perl and TCL is a plus.
• Good theoretical and practical understanding of digital signal processing and data recovery circuits is required.
• Good communication skills for interacting between different design groups and customer support teams are required.
• Must be self-motivated, proactive, and able to balance great design with meeting tight deadlines.
• Must exhibit ability to produce exceptional results as an individual and team contributor.