Application Engineer – Formal Verification

Cadence Design Systems is looking for a candidate to be part of its Technical Field Operation (TFO) team in Belo Horizonte-MG. Cadence has been nominated as a Great Place to Work globally and in Brazil, and is also a Fortune 100 Best Companies to Work For.

Job Description:

• Be responsible to provide technical support, helping Cadence customers to effectively deploy our industry leading Verification products.
• You will be in a team working with our customers to understand their needs and provide guidance on the best technologies and methodologies to enable their success, coming up with innovate solutions to address our customers’ most challenging problems.

This role will be focused on Cadence products on the Formal Verification domain: Jasper Formal Verification platform and other Jasper tools and apps.

Requirements:

• Complete Bachelor or graduation Computer/Electrical Engineering or related areas;
• Good RTL understanding and coding (Verilog, VHDL);
• Excellent English written and oral communication skills;

Nice to have Skills

• Knowledge of Unix
• Design fundamentals such as architecture, micro-architecture, HDLs Synthesis and timing
• Verification skills such as testbench development and debug, SystemVerilog, SVA
• Scripting languages (Tcl, Bash, Perl, Python, etc)

Additional Job Details:

• Employment category: CLT
• Employment term: 40 hours/week
• Location: Avenida do Contorno, 5800 – Savassi – Belo Horizonte/MG

About Cadence Design Systems:

Cadence is the only company that provides the expertise and tools, IP, and hardware required for the entire electronics design chain, from chip design to chip packaging to boards and to systems. We enable electronic systems and semiconductor companies to create innovative products that transform the way people live, work, and play. Our products are used in mobile, consumer, cloud datacenter, automotive, aerospace, IoT, industrial and other market segments. For more information, access http://www.cadence.com.