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Designing at 7nm with ARM, MediaTek, Renesas, Cadence and TSMC

Designing at 7nm with ARM, MediaTek, Renesas, Cadence and TSMC
by Daniel Payne on 07-11-2017 at 12:00 pm

The bleeding edge of SoC design was on full display last month at DAC in Austin as I listened to a panel session where members talked about their specific experiences so far designing with the 7nm process node. Jim Hogan was the moderator and the panel quickly got into what their respective companies are doing with 7nm technology already. Earlier this year we heard about the first 10nm chip being used for the Qualcomm Snapdragon 835 chip, so I was quite interested to here what the next smaller node at 7nm was going to bring us.

Rob Christy, ARM – They’ve been designing at 7nm for one year now, and are focusing on mobile processors.

Anand Rajagopalan, MediaTek – They develop chips for the mobile space, about 50% of Internet traffic is now coming from mobile devices like phones and tablets. Multi-core chips now have multi-GHz clock speeds thanks to 7nm. Mobile gaming is their biggest sector because it demands the highest frame rates along with sophisticated shading effect. Consumers really want a mobile device with dual cameras and higher bandwidth, so the need to use 7nm is there, meeting the user expectations.

Kazuhiro Takahashi, Renesas– This Japanese semiconductor company is a solutions provider to several markets: auto, office automation, home electronics. They need 7nm silicon to provide competitive solutions.

Tom Quan, TSMC –Both smart mobile and automotive markets are driving the development of new nodes for the highest performance. HPC and cloud data center are some emerging markets that also benefit from 7nm. They have been working on 7nm for 2 years now, it has entered into risk production now, with full volume planned for next year. There are 30 customers so far with 7nm now. Automotive also needs 7nm for ADAS because of all that local processing is required for self-driving cars and driver assistance features.

Mitch Lowe, Cadence– There’s been a high demand for leading edge customers using EDA tools in complex markets like: data center, networking, mobile, auto. At Cadence they work to get specific EDA tools qualified on 7nm flows. Some of the EDA tools are using machine learning to provide better results. The Cadence EDA tools are ready for production with 7nm, including libraries, IP blocks and memories.

Jim then started the Q&A session.

Q: Why move to 7nm technology and what are the benefits?

A: Anand – we needed the raw compute power for mobile devices with 7nm, along with bandwidth and graphics performance.
A: Kazuhiro – we wanted to get better performance and lower power, along with running demanding graphics applications.

Q: Is 7nm ramping fast?

A: Tom – compared to 16nm+, it will be 35-40% faster, 60% lower power, 3.3X more dense. SRAM memories are about .37X smaller. Cadence tools were certified in March for version 1.0 PKD, and we expect to see some 18 tape outs this year. Volume production is planned for 2018.

Q: What is the risk to making IP work?

A: ARM – we decided to skip the 10nm node, so it was no big surprise going to 7nm in creating physical IP. DRC runs were certainly a big challenge and creating power grids has become more difficult.

A: Mitch – our IP team worked closely with TSMC to be more productive. At 7nm the Mixed-signal IP still has big digital content. The cells are smaller, but routing has been the big challenge along with power/ground grids.

Q: Are ultra low VDD supplies being used?

A: Tom – Yes, we see chips going down to 0.6V on VDD, so then the variation effects come into play. Cut masks are another new requirement at 7nm.

Q: What challenges are you seeing at 7nm?

A: Kazuhiro – Automotive benefits from the lower power provided at 7nm, however wire resistance effects cell delays greatly, so timing optimization becomes more critical.

A: Anand – We need to meet our power budgets, and the grid routing is difficult at 7nm. DRC needs to be taken into account with early floor planning now up front, not at the last minute like with larger nodes.

Q: What other challenges are you facing with design at 7nm?

A: Rob – Much of the IoT market can continue to use the 45 nm node because of cost requirements. Leakage and power are much improved from 16nm down to 7nm. You must plan more stringently at 7nm because DRC runs take too long and we cannot manually fix DRC violations, it must be automated and really correct by construction only.

A: Anand – the tools need to be DRC ready up front. Wires are important and the resistance values need to be managed. There’s really no room for hand editing at 7nm. The tool flows need to be timing aware, DRC aware and sign-off ready.

A: Renesas – timing closure is the hardest challenge for us.

A: Tom – cut metal is needed to meet density goals. Resistance of wires dominates the speed of 7nm chips. We can minimize M1 routing to improve speeds, but then the vias start to limit speed. We use a via pillar instead to get lowest resistance. Does P&R know about how to use a via pillar? Synthesis tools needs to understand via pillars too, probably for the first time.

Q: How does Cadence help meet these requirements?

A: Mitch – Machine learning is helping out for congestion analysis and P&R for predictability. Synthesis uses the same engine throughout the process. Automatic wide wires and spacing is used to automatically meet DRC rules. Clock specific rules have also been automated.

Q: What do you want from IP partner?

A: Tome – an early test chip needs all essential IP cells like foundation cells and Interface IP.

Q: Does Renesas need something from ARM to be successful?

A: Kazuhiro – Reliability related issues need to be addressed early on for a new node like 7nm.

A: Anand – from architecture to implementation we need better early physical planning to meet our specs.

A: Rob – use of the via pillar is critical to building clocks. EM is a big reliability issue for our clocks. Wiring is a huge problem, especially at the lowest levels because it’s not scaling well for resistance. DRCs also need to be included in the optimization loop.

Q: Am I going to lose my job at 7nm?

A: Tom – IC design is doable at 7nm, it will be another long lasting node, and it has the fastest ramp in order to meet demand for mobile and HPC/cloud/self driving cars.

A: Renesas – we are confident to use 7nm in our designs, but where is EUV at 7nm?

A: Tom – N7+ will be our first process to use EUV layers, stay tuned in 2018 when it’s ready.

A: Anand – we need both the tools and the flow to be optimized for our first design.

A: ARM – we have no reservations about 7nm designs. EDA tools are mature for this node and in 2018 to see more customer results.


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