Arm Total Design Hints at Accelerating Multi-Die Activity

I confess I am reading tea leaves in this blog, but why not? Arm recently announced Arm Total Design, an expansion of their Compute Subsystems (CSS) offering which made me wonder about the motivation behind this direction. They have a lot of blue-chip partners lined up for this program yet only a general pointer to multi-die systems and what applications might drive the need. Neither Arm nor their partners will make this investment simply for PR value, so I have to assume there is building activity they are not ready to announce. I’m guessing that in a still shaky economy the big silicon drivers (in hyperscalers, AI, automotive, and maybe communication infrastructure) are already engaged in faster and managed cost paths to differentiated custom silicon, likely in multi-die systems.

Arm CSS and Total Design

I wrote about CSS recently. CSS N2, as Arm describes it, is customizable compute subsystem that is configured, verified, validated and PPA-optimized by Arm. Think of a multi-core cluster objective for which you don’t just get the Lego pieces (CPU core, coherent interconnect, memory subsystem, etc.) but a complete customizable compute subsystem configured with up to 64 Neoverse N2 cores, multiple DDR5/LP DDR5 channels and multiple PCIe/CXL PHY/controller. All verified, validated, and PPA-optimized by Arm to a target foundry and process.

Most recently Arm revealed Arm Total Design, a comprehensive ecosystem of ASIC design houses, IP vendors, EDA tool providers, foundries, and firmware developers – to accelerate and simplify the development of Neoverse CSS-based systems. EDA tools and IP are supplied by Cadence, Synopsys, Rambus and of course Arm, among others. Design services come from companies including ADTechnology, Alphawave Semi, Broadcom, Capgemini, Faraday, Socionext and Sondrel. For silicon process and packaging technology they call out Intel Foundry Services and TSMC (though not Samsung curiously, maybe they are still working on that partnership). And AMI is in this ecosystem to provide software and firmware support.

Reading the tea leaves

I recently blogged on a Synopsys-hosted panel on multi-die systems which suggested already at least 100+ such systems in development. Representatives from Intel and Samsung voiced no objections to that estimate. At the same time there was consensus that these are technologies still very much in development, requiring close collaboration between system company, EDA, IP, chiplet, design services, foundry, and software development. This is not something that an in-house design team, even a hyperscaler design team, can handle on their own.

Arm mentions multi-die chiplet SoC designs in their release though in a fairly general way as the next frontier. I suspect the need is more pressing. Multi-die systems are becoming essential to support state of the art designs driven by the latest AI innovations, especially around transformer-based techniques. We already know that datacenters are pushing these technologies, automotive applications are looking for differentiation in improved natural language recognition and visual transformers for better global recognition, even wireless infrastructure sees application for more intelligent services and more efficient radio communication.

All these applications are pushing higher levels of integration between compute, accelerators and memory, the kind of integration which requires multi-die packaging. This demands experts from foundries to design services to EDA tooling. We also need a ramp-up in available high value chiplet designs, where the press release suggests another hint. Socionext have built a multi-core CPU chiplet around CSS and are aiming it at TSMC 2nm for markets in server CPUs, data center AI edge servers, and 5/6G infrastructure.

More momentum behind multi-die systems. You can read the press release HERE.