Did we forget non-volatile memory?

In our rush to shrink SoC nodes more and more to achieve better performance and more complex devices, we may have forgotten a passenger in the back seat: non-volatile memory. There has been little discussion of this in the pages of SemiWiki until now. Let’s give it a closer look.

Embedded flash has usually been associated with microcontrollers, replacing ROM as the code storage mechanism and offering reprogrammability. MCUs have been on less aggressive nodes for a number of reasons, including integrated mixed signal circuitry, and enough density on mature nodes to achieve high yields and a very low cost.

The lines between SoC and MCU are blurring, now lining up with whether a core has an MMU or not. For larger code and data storage requirements, discrete flash is still a choice – and it ran into problems first.

Discrete NAND flash fabrication was happily on the path of most shrinkage. Then, issues developed as we arrived at 1x nm processes: reliability and endurance started dropping, rapidly. Noise started affecting cells packed too closely together. Write endurance, always a lurking concern with flash, became a problem as smaller cells wear out faster.

The problem with planar 2D NAND flash is now so bad, we are at the end of the line as far as process shrinks. The solution is 3D vertical NAND, or V-NAND. Relaxing geometries back to 3x nm ranges to get past the noise and wear issues, V-NAND stacks cells vertically in channeled layers to expand capacity. Scalability relies on increasing the number of vertical layers, instead of shrinking the geometry.

V-NAND presumably solves the issues for discrete flash, but does little for embedded flash. The V-NAND process is so radically different from those used for SoCs, it is hard to see V-NAND flash ever co-existing on an SoC outside of a stacked 3D-IC approach.

Similarly, a few MCU manufacturers are moving toward FRAM for integrated non-volatile memory. FRAM is fast, very durable, and low power – if it can be fabricated reliably, with exotic materials in the mix. It also does not scale in capacity or geometry very well, but may be more than adequate for MCU architectures on mature nodes.

Embedded flash is not as easy as it sounds. A quick scan shows the most advanced node disclosed publicly is Renesas, teamed with TSMC for embedded flash at 28nm. Getting beyond that point may expose exactly the same problems discrete flash has already run into at smaller geometries.

One-time programmable (OTP) antifuse memory, such as Sidense SHF, is headed for 16nm FinFET as we covered last month. OTP can emulate reprogrammability using multiple blocks for code storage. It also provides enhanced security against reverse engineering, and more than enough read endurance and reliability.

What’s the solution? As badly as we’d like a single non-volatile memory bullet, there may not be one at sub-20nm for a while.

When OTP is working at 16nm, it will go where embedded flash has not ventured yet. Not enough reprogrammability cycles for code storage? If you are reprogramming production code more than about 10 or maybe at the worst 20 times over the life of an embedded device, you don’t need better non-volatile memory, you need better programmers and QA folks.

Yes, the model of pluggable apps such as used in Android does present issues – that use case is probably best for large external discrete flash, anyway. We’re assuming a class of SoC emerges needing the performance that sub-20nm offers, but running a more MCU-like application with embedded code.

The tradeoff of OTP may be with serial SPI flash – slower (you went to sub-20nm for a reason, executing code out of SPI would be undoing that), but able to capture data written frequently. The question becomes if data really needs to be non-volatile. Configuration data is well served with OTP, but if the requirement is writing a continuous data stream from a sensor or other source, serial SPI flash may be necessary.

It is an interesting tradeoff. The point of this is not to overlook integrated OTP NVM for code storage and configuration data requirements, because the assumption of embedded flash existing for all non-volatile needs may not be valid as geometries continue to shrink. Never say never, but right now it is a problem at and beyond 28nm.

How are you thinking about this issue? Have you rediscovered OTP NVM for code storage? What about data storage? Do we need research on another non-volatile memory technology for advanced nodes? Or is there just no reason to ever head south of 28nm for some applications?

Related articles:

• Sidense overlays OTP on TSMC 16nm FinFET

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