Hardware security is essential for high-performance computing (HPC), AI, and Edge IoT applications when designing SoCs in advanced process nodes. These designs include Gigabits of SRAM and require storing >16Kb …
Join us for an insightful presentation into the integration of Synopsys Verdi® and Euclide IDE, revolutionizing the debugging landscape for hardware designers. In this session, we’ll delve into next-generation Verdi’s …
Continue reading "Webinar: Unlocking Next-Gen Debugging: Synopsys Verdi and Euclide IDE Integration"
The adoption of wide-bandgap power MOSFETs (SiC and GaN) is growing in power electronic applications for consumer electronics, automotive, and renewable energy. Successful implementation of simulation in system design requires high-fidelity, numerically robust, and compact power MOSFET models. The Saber circuit simulation environment offers a proven and mature solution with a dedicated tool that allows …
In recent years, the semiconductor industry has experienced a breakthrough in the onset of 2.5D and 3D chiplet-based products. These products promise to extend the limits of Moore’s Law while demolishing limitations on speed and capacity for our highest tiers of compute. But for all the adulation we heap upon the 3DIC paradigm, we seemingly …
ASIP Designer enables the creation of custom vector DSPs for AI Wednesday, May 22, 2024 4:00 - 6:00 pm CEST / 7:00 - 9:00 am PT Case Studies accelerating AI applications using custom RISC-V based SIMD/VLIW DSPs The revolution in AI triggers an increased awareness for application-specific instruction-set processors (ASIPs). These processors implement a specialized …
Synopsys' SLM PVT Monitor (process detector, voltage monitor, temperature sensor) IP can collect voltage, temperature, and process parameters from different blocks within the IC in real time. These data can be analyzed and used to take meaningful action to optimize the performance of the chip at any stage of silicon lifecycle. This webinar focuses on …
Continue reading "Webinar: Reimagining Synopsys SLM PVT Monitoring IP for Advanced Node GAA Process"
Thursday, May 30, 2024 | 10:00-11:00 a.m. PDT Many automotive applications require processing workloads with minimum latency and precise timing budgets. This is especially true for safety-critical applications like adaptive …
Today’s advanced node chip designs are faced with many new complexities which require more verification, more validation and more analysis. The resulting data from these added steps has also grown exponentially and engineers need a way to efficiently analyze this information. The result is a new paradigm shift which has led to data overload requiring …
The digital chip design flow carries with it an enormous wealth of untapped information regarding the health and status of your SoC design. The ability to efficiently mine this data …
Continue reading "Webinar: Maximize Productivity with Deep Insights into PPA Trajectories"
The challenges before semiconductor fabs are expansive and evolving. As the size of chips shrinks from nanometers to eventually angstroms, the complexity of the manufacturing process increases in response. To …
Connecting the Synopsys User Community Since 1991, the Synopsys Users Group (SNUG) has represented a global design community focused on innovating from Silicon to Systems. Today, as the electronics industry’s largest user conference, SNUG brings together over 12,000 Synopsys tool and technology users across North America, Europe, Asia, and Japan. In addition to peer-reviewed technical …
Connecting the Synopsys User Community Since 1991, the Synopsys Users Group (SNUG) has represented a global design community focused on innovating from Silicon to Systems. Today, as the electronics industry’s largest user conference, SNUG brings together over 12,000 Synopsys tool and technology users across North America, Europe, Asia, and Japan. In addition to peer-reviewed technical …
