The fourth installment of DVCon India took place in Bangalore, September 14-15. As customary, it was hosted in the Leela Palace, a luxurious and tranquil resort in the center of Bangalore, and an excellent venue to host the popular event.
As reported in my previous DVCon India trip reports, the daily and evening traffic in Bangalore is horrible, and a dramatic contrast to the empty roads in the middle of the night when overseas travelers arrive or leave the country. Congested roadways forced conference management to delay the beginning of the event by 30 minutes to accommodate the slow arrivals of the participants.
The mornings of the two-day conference included keynotes and panels. The two-day afternoons were packed with 13 tutorials, 39 papers, and nine posters. Sessions covered various aspects of the design verification processes, from electronic system level (ESL) to design verification (DV), the majority focused on UVM, formal, and low power with an eye on safety in automotive chip design. Hardware/software co-verification and portable stimulus were also covered.
The conference kicked off with a keynote address by Chris Tice, vice president of Verification Continuum Solutions at Synopsys, titled “The Peta Cycle Challenge.” For the mathematically challenged, probably none among the highly educated Indian engineers, it equates to 10^15, or a quadrillion cycles. The presentation started with a set of case studies from different segments of the electronic industry that proved the need for peta cycles for thorough design verification/validation. Rather interesting stuff. Unfortunately, the presentation turned into a sales pitch for the Synopsys’ Verification Continuum with emphasis on emulation and FPGA prototyping that did not belong to a keynote. By the way, I wonder why Synopsys has not supported Chris’ statement “emulators based on commercial FPGAs have a refresh rate of two years versus the four/five years of the custom-hardware-based counterparts.” After all, the yet-to-be announced next generation of the Synopsys’ ZeBu emulator based on commercial FPGAs lags already almost four years behind the launch of the Xilinx UltraScale in December 2013.
Mr. Tice’s keynote was followed by an invited keynote titled, “Re-emergence of Artificial Intelligence Based on Deep Learning Algorithm,” delivered by Vishal Dhupar from NVIDIA. Mr. Dhupar traced the similarities in the evolution of self-driving cars, drones and robots as the result of deep learning, a fast growing field in artificial intelligence.
Following Mr. Dhupar’s insightful comments were two more invited keynotes. Manish Goel from Qualcomm India discussed “System-level Design Challenges for Mobile Chipsets,” and Apurva Kalia reviewed the evolution of the self-driving car in his “Would you Send Your Child to School in an Autonomous Car?” presentation.
Two panels, one on ESL and the other on DV, concluded the first morning. I moderated the DV panel, titled “Hardware Emulation’s Starring Role in SoC Verification.” Panelists included Sundararajan Haran of Microsemi; Ashok Natarajan from Qualcomm; Ravindra Babu of Cypress; and Hanns Windele from Mentor, a Siemens Business. All shared their views on the evolution of emulation in the design verification flow. A write-up summarizing the experiences and opinions of the panelists will follow shortly.
The keynote on the second day was delivered by Ravi Subramanian of Mentor and titled “Innovations in Computing, Networking, and Communications: Driving the Next Big Wave In Verification.” First, Mr. Subramanian using several data points pointed out that recent semiconductor industry structural changes are about specialization, not consolidation. He then showed that a growing captive semiconductor market is emerging in system houses. For example, MEA (More Electrical Aircraft) is disrupting the aircraft industry via electrification and automation of the entire airplanes. This was followed by an analysis of the convergence of, and key trends in computing, networking and communications. According to Mr. Subramanian, convergence is posing a big challenge in functional verification, forcing the industry to rethink its approach.
As a nice touch, Mr. Subramanian complimented the Indian engineering community, said to lead the worldwide adoption of the SystemVerilog design language and the UVM design methodology.
An invited keynote titled, “Disruptive Technology That Will Transform The Auto Industry,” was presented by Sanjay Gupta, vice president and country manager at NXP. It was an impressive talk supported by lots of interesting data. Unfortunately, keynotes’ slides were not made available to the attendees. I would kindly ask the DVCon/India committee to make them available in future events.
On the exhibit floor 15 EDA companies demonstrated their verification tools and methodologies. The vendors list included the big three –– Cadence, Mentor and Synopsys ––as well as Aldec, Breker, Chipware, Circuit Sutra, Coverify, Doulos, SmartDV, TVS, Thruechip, Verifast, Verific, and Verifyter.
DVCon India 2017 was a successful conference, crammed with useful information, and a great networking opportunity. As usual, the Indian hosts were cordial and humorous.
The 2017 round of DVCon conferences organized by Accellera will conclude with DVCon Europe in Munich, Germany, October 19-20.Share this post via: