This year for the first time the Thursday of DAC is tranining day. So that would be June 6th in Austin, of course. There are four tracks of training focused on SystemC, ARM Cortex and two on SystemVerilog, all areas of increasing use in SoC design, especially in mobile.
Each track of training is divided into two parts, one held from 9am to 12.30pm, and then a second part from 2pm to 5.30pm. All sessions are taught by a professional educator from Doulos (along with an engineer from ARM for the ARM track) who is the global leader in the development and delivery of training solutions for engineers creating electronic products.
The four tracks are:
- Track 1: SystemVerilog
- Part 1: Synthesis-Friendly System Verilog.
- Part 2: A Hardware Designers Guide to SystemVerilog Verification
- Track 2: SystemVerilog Verification
- Part 1: Hardcore SystemVerilog for Class-based Verification
- Part 2: Getting Started with UVM, the Universal Verification Methodology
- Track 3: ARM Accredited Engineer Program
- Part 1: Kick Start to the ARM Cortex Processor Family
- Part 2: Software Development for the ARM Cortex Processor Family
- Track 4: ESL and SystemC, the Definitive Guide to SystemC
- Part 1: The SystemC Language
- Part 2: TLM 2.0 and the IEEE 1666.2011 Standard
Details of all the training courses, including summaries and presenter biographies and room numbers, are all on the DAC website here. You can sign up for one of the training courses when you register for DAC.
Doulos also produce Golden Reference Guides to these sorts of topics:
- UVM – Full Edition, supporting version 1.1.
- VMM fully supporting version 1.2.
- OVM fully supporting OVM 2.0
- SystemC IEEE 1666™-2006 compliant, supporting version 2.2
- SystemVerilog supporting SystemVerilog IEEE Std 1800™-2009
- PSL supporting v1.1
Details of the guides are available here. They are $50 each.Share this post via: