Every year in Monterey is a relatively small conference that looks at the design process, EDPS, the electronic design process symposium. I gave a keynote there a couple of years ago, but you don’t have to listen to me this time. The keynotes are from:
- 1st day: Misha Buric, CTO of Altera, talking about SoC FPGAs and other things
- Dinner: Jim Hogan, himself, talking about SoC Realization
- 2nd day: Riko Radojcic, director of engineering at Qualcomm, talking about 3D IC roadmap
I highly recommend this conference. It covers a lot of different issues. The second day, in particular, covers a lot of information on 3D ICs which is clearly a hot topic. Silicon interposer ICs and memory on processor are clearly arrived, and true 3D ICs will be coming, especially if EUV isn’t ready for full production by 14nm.
The first day is everything that isn’t 3D. After Misha’s keynote are the top 5 problems of EDA:
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After lunch, there is a panel session on EDA in the cloud with:
- Hans Spanjaart of Altera (moderator)
- James Colgan of Xuropa on the CADless semiconductor company
- Don MacMillen of Nimbic on electromagneic simulation in the cloud
- Kiron Pai of Intel on improving producitivity in the cloud
- Azadeh Davoudi of University of Wisconsin on highly distributed global routing
- Naresh Seghal of Intel on optimizing a cloud
Gary Smith reviews the new ITRS power model which took longer than expected to produce but was finally announced in January this year.
Ian Ferguson of ARM on energy efficient servers in the data center (let me guess, ARM ones).
Qi Wang of Cadence on whether the power problem is solved (I’d say not yet).
Grant Martin of Tensilica on another mysterious unannounced topic but if I had to guess it would be something to do with offloading the control microprocessor (usually ARM) with specialized VLIW processors optimized for the task at hand.
Then off to the wharf for dinner and Hogan.
Next day kicks of with Riko’s keynote and then a series of 3D IC design topics:
- Stephen Pateras of Mentor on BIST for 3D ICs
- Arif Rahman of Altera on FPGA design challenges, presumably 3D ones
- Samta Bansal of Cadence on the wide-IO standard for putting memory stacks on processors
During lunch there is a 3D IC panel moderated by Steve Leibson:
- Herb Reiter
- Samta Bansal of Cadence
- Dusan Petranovic of Mentor
- Deepak Sekar of Monolithic 3D
- Steve Smith of Synopsys
And with that we wrap up and most of us drive back north.
Next Generation of Systems Design at Siemens