Webinar: Hardware Verification using VirtuaLAB

VirtuaLAB protocol solutions offer a full-stack testing environment with seamless connectivity and stimulus traffic generation for designs under test. It operates autonomously, adapting to scenarios without requiring protocol knowledge from the user. VirtuaLAB significantly reduces test and compliance suite regression times, running at high emulation speeds, integrated with Protocol Analyzer for complete protocol visibility and performance metrics. Supporting any scenario, it enables users to focus on their design’s unique value while ensuring reliable standard protocol interactions.

Who Should Attend:

• Engineers and Managers responsible for System Design Verification of complex SoCs
• Engineers and Managers responsible for design performance verification

What you will learn:

• Attendees will learn how VirtuaLAB protocol solutions provide a full stack from the physical to the application layer to connect to your design under test and create stimulus traffic as a host, or respond to commands in the form of a compliant device.
• Attendees will learn the ease of bring-up of a VirtuaLAB environment with no testbench required, but how to use real-world software to create workloads exactly matching the end-user of your silicon.
• Attendees will see a demonstration of VirtuaLAB running a back-to-back UFS4 host model and RTL SSD model DUT, running the LLAMA 3.1 LLM, and providing query responses in real-time.

REGISTER HERE