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Webinar: Efficient and Robust Memory Verification in Modern SoCs Using Formal Equivalence Checker
November 13 @ 8:30 AM - 9:30 AM
With the increasing complexity and importance of memories in modern ICs, there is a clear need for specialized tools and techniques for the design and verification of embedded memory blocks. Traditional methods like SPICE simulation and cell-based formal verification have limitations; SPICE offers circuit-level accuracy but limited coverage, while cell-based methods can’t fully represent transistor-level behavior. Synopsys ESP, a custom circuit formal equivalence checker, addresses these challenges with its patented symbolic simulation technology, combining the power of formal methods with event-driven simulation for sequential equivalence checking. This approach dramatically enhances the quality of functional verification and boosts verification productivity.
Join our webinar to explore how Synopsys ESP provides a circuit-aware, easy-to-use solution for memory verification. An overview on ESP is provided along with Intel sharing their success using ESP for Content Addressable Memory (CAM).
Agenda
- ESP Overview (10-15 mins) presented by Almitra Pradhan, Synopsys
- Intel usage of ESP for CAM (20-25 mins) presented by Anshuli Pandey, Intel
- Summary
- Q&A
Speakers
Listed below are the industry leaders scheduled to speak.
Anshuli Pandey
Circuit Design Engineering Manager
Intel
Anshuli Pandey is Circuit Design Engineering Manager in Central Memory Organization team in Intel. This team is responsible for providing Register File, ROM, Content Addressable Memory compilers for internal products and Foundry Services platform. She is an alumnus of BITS Pilani and has ~19 years of experience in Memory Design. She has submitted many papers in Intel internal conference over the years.
Almitra Pradhan
Sr. R&D Manager
Synopsys
Almitra Pradhan leads the ESP product development at Synopsys. She has 15 years of experience in EDA specializing in Transistor level EDA tools for custom digital design. She holds a Ph.D. from University of Cincinnati, Ohio in Electrical and Computer Engineering.
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