USB is certainly the most ubiquitous of the Interface protocols, used in our day to day life to connect multiple systems, as well as in professional segments like industrial or even high performance servers (yes, these systems integrates USB 3 connections). But USB is also one of the protocols able to generate frustration every day. I am not talking about strong frustration, just one of the small issues we are facing several time a day when plugging USB connector the wrong way! Then we think that it shouldn’t be rocket science to define a reversible connector, that you can plug it either way…but we will see that it requires high level engineering skills.
This magic connector has been finally defined by USB-IF, it’s the Type-C connector and I was told by Synopsys that the Type-C specification is the fastest adopted USB specification of all time: it took only 7 months between the spec and the product release. If you consider that we have waited 20 years to benefit from a reversible connector, fulminating against this #%&@ connector, this fast adoption make sense.
IPnest delivering the “Interface IP Survey” every year since 2009, I know that Synopsys is the undisputed leader on the USB IP segment, but I didn’t knew about the cumulated number of USB IP projects won by Synopsys: almost 3,500 since 1995. As the clear leader on this USB IP segment, Synopsys had to position as quickly as possible to support USB-C IP.
USB-C connector has to be reversible. Which is easy to use and to understand has a pretty strong impact on the USB IP itself, as the USB PHY is concerned. If you are familiar with interface IP, you know that it can be split into a pure digital block, the controller, and a mixed-signal part, the PHY. Because the PHY is mixed-signal, it’s 100% process dependent. In other words, it’s almost impossible to support all foundries and all process nodes and the multiple variations for a process node (LP, HPM, etc.) immediately. Synopsys has started by the most challenging, the USB-C 3.1 PHY running at 10 Gbps designed on 14/16 nm FinFET technology node, targeting the high end market (Application Processor for Mobile, Tablets or Laptop), as well as the mainstream with USB-C PHY IP supporting 3.0 and 2.0 designed on 14/16 nm FinFET and 28 nm Bulk technology nodes. That’s why you can see two different USB-C PHY IP on the picture below. Redesigning these PHY IP has been the opportunity for Synopsys to optimize it for area, so it counts up to 40% less pin, leading to a smaller footprint.
As I have previously mentioned, the Type-C connector impact the USB PHY. If you want to implement USB-C, you will have to implement the controller too. Thus you will expect Synopsys to have validated the interoperability of the USB 3.1 controller (supporting also 2.0 and 1.1 for backward compatibility) with these new PHY IP. Such work being done internally, the next step for the company was to validate the interoperability of the complete USB-C solution during the USB-IF plug-fest (compliance program) in July 2015, were you can verify that your solution is compliant and interoperable.
It’s crucial for a Synopsys customer that the USB-C IP has passed the compliance test, but it may also be very important to benefit from USB 3.1 Verification IP (to validate the proper integration of the IP into the SoC) and comprehensive Prototyping Kit (below) to allow as early as possible software development, in parallel with the SoC integration. Important to mention, Synopsys customers can use their existing USB 3.0 drivers to support the new USB 3.1 controller IP, this controller has been built on the existing USB 3.0 controller.
Synopsys is launching the first USB Type-C IP solutions supporting USB 3.1, 3.0 and 2.0 specifications, built on USB PHY IP proven in literally 100’s of customer designs. Last point, but not least: USB Type-C has been specified to deliver power up to 100 Watts!! Clearly USB Type-C PHY IP design has to be robust, on top of running at 10 Gbps.Share this post via: