AMS Panel: Micronas, Infineon, AMD, STMicro

Synopsyshosted an AMS Luncheon panel today at DACin the Westin Hotel and invited four customers to talk about their actual design challenges and experiences. I’ve typed up my notes from this event.

Farhad – product name of VCS AMS (VCS plus CustomSim), both digital and FastSPICE simulators together. New technologies extend to mixed-signal: Real number modeling, ams testbench, native low power.

Micronas– Dr. Gernot Koch, CAD Team manager. Automotive and industrial sensors, with 900 people worldwide, design, package and test devices. Hall sensors (100K transistors, 60-100% analog) and HV controllers (ARM cores, DSP, analog, 700K transistors).

The goal is zero PPM because of safety-driven requirements. Emphasis on verification both functional and performance.

Types of simulation: Full SPICE (use FineSim), Verilog and SPICE, Verilog and Verilog AMS, discrete realtime modeling (pure digital plus wreal elements).

To make wreal modeling work they use the Verilog wire network for both digital and analog behavior, added their own custom PLI to support analog/digital but now they use VCS AMS instead for simulation. Fastest simulation results are with discrete real-type models.

Writing AMS models does take time, typically 2 days when starting from a netlist topology. The modeling effort is worth it because it reduces silicon re-spins.

Infineon– Haiko Morgenstern. Power-aware mixed-signal SoC design projects. They serve worldwide markets for automotive, security (ID cards, pay tv cards, NFC) and energy efficiency (renewable energy, building & Factory automation).

Their analog blocks are created as full-custom blocks, then used within a digital system (semi-custom design flow). They needed a mixed-signal verification design flow, so decided to use the VCS AMS simulation combination. Also simulated with CustomSim XA for analog blocks along with VCS/VCS-MX on digital (uses direct kernal integration). SPICE is simulated on top, then instances of ARM core in digital, memory, analog macros for sensors, CAN and LIN.

Used the CustomSim CIrcuitCheck (CCK) to automate AMS verification runs. SImulated the power-up sequences to verify that the power management unit is functioning properly, also simulated power-down and wake-up behaviors (all over milliseconds of actual time) to ensure high reliability prior to tape-out.

Want to see – one environment for debug of both Analog and Digital, not separate. Support UPF flow from Infineon, save and restore for VCS AMS, want more speed with FastSPICE CustomSim for multi-threading algorithms.

Mei-Cheng Huang, AMD– their group does design of SerDes PHYs in 28nm down to 14nm nodes. They need to support AMS protocols and IP like: SerDes, SATA, DDR, Clock Data Recovery, Delay Loop Lock, Phase Interpolator, Phase Locked Loop.

They use the UVM and OVM methodologies to guide their verification efforts for AMS blocks and IP.

Verification challenges: multiple voltage domains, multiple clock domains, avoid circuit contention, closed-loop feedback between digital control state machine and analog design blocks, viewing analog signals during simulation, simulation run times .

A UVM infrastructure is used for test bench, Device Under Test, stimulus generation, measurements. Both SPICE and Verilog models are used in verification.

There is a voltage domain checker tool, clock domain crossing verification is done using synchronizers, write RTL assertions to verify proper operation of signals and contention. The VCS AMS simulator is used throughout their design and verification efforts. They even have self-checking routines for AMS blocks.

AMD has used VCS AMS on both 28nm and 20nm designs so far, widely adopted. Good simulation speed and accuracy trade-off with multi-core CustomSIm.

On SerDes PHY they use a Verilog (on top) testbench approach.

Both UVM and OVM approaches used on AMS designs with the VCS AMS simulator.

What they need – more speed at transistor levels. Cross module referencing support required.

High-speed PHY designed with VCS AMS simulator, and await more speed improvements in the future.

Pierluigi Daglio – STMicroelectronics. Managing the SmartPower design enablement group. There are two different scenarios at ST: transistor-level simulation for IP, full-chip simulations.

Large IP blocks and macro-cells: use transistor-level simulation, ERC, Safe Operating Areas (SOA), model in Verilog-A.

Complete system simulation requires digital and analog co-simulation. Start with a digital test bench, instead of an analog test bench. HDL used for digital, Verilog-A and Verilog-AMS used for analog blocks.

Using Analog on Top for system-level verification flow.

Use CustomSim for transistor-level circuit simulation. AMS simulation done with VCS AMS or CustomSIm plus another HDL simulator. It’s easier to stick with Synopsys and use VCS AMS, instead of two vendor simulators connected together.

The difference between AMS simulators is always limited by their FastSPICE simulator, not the HDL engine.

A chart showed simulation performance versus accuracy: SPICE, FastSPICE, Verilog-A, Verilog-AMS, VHDL-AMS, Real Wreal, Digital. With VCS AMS you can combine any of these simulation engines as needed.

For their AMS verification they use Analog on Top, digital test bench in VHDL, then DUT is both digital and analog instances. Being able to save then restore the state of an AMS simulation is often used, and can save simulation times (ie. power up sequence saved, then restart from that state and do multiple verifications).

STMicroelectronics choose VCS AMS over other simulators because of: no need for wrappers, best simulation speed, back-annotation supported, intuitive GUI, flash cell modeling, save & restore. Still want to see improvements in the Synopsys GUI, more flexibility in save/restore wanted.

lang: en_US

Share this post via:

• 
• 
• 
•