#50DAC: Winning in Monte Carlo!

One of the places you will be able to find me at the Design Automation Conference (DAC) is on the speaker panel for a Monday Tutorial – Winning in Monte Carlo: Managing Simulations Under Variability and Reliability. Having worked closely with TSMC, GLOBALFOUNDRIES, Solido Design Automation, and some of the top fabless semiconductor companies, I have first hand experience with the increased variation at advanced process nodes and the increased SPICE simulation burden that results. Variation analysis and design software is absolutely being used by semiconductor companies and foundries to cut down on these SPICE simulations by intelligently figuring out what to simulate. This tutorial will give practical insight into causes of and solutions for variability and reliability. I highly recommend it.

Thanks to FinFETs and other process innovations, we are still shrinking devices. But it comes at a steep price: variability and reliability have become far worse, so effective design and verification is causing an explosion in simulations. First, Dan Nenni will do the introductions and present process variation content and analytics from SemiWiki.com. Presenter Prof. Georges Gielen from KU Leuven University will describe CAD and circuit techniques for variability and reliability. Next Yu Cao from Arizona State University will describe how at 20nm and new features from FinFETs, double patterning, interconnects, and other process innovations will require deep knowledge of variability and its relation to performance. More corners and statistical spreads will come into play, so advanced IC design tools will be needed to minimize design cycle times. Then, Trent McConaghy CTO of Solido Design Automation, will describe industrial techniques for fast PVT, 3-sigma, and high-sigma verification. Finally, Ting Ku, Director of Engineering at Nvidia, will describe a signal integrity case study using variation-aware design techniques.

Here is a preview of my intro slides:

Sources of Variation @ 28nm
•Random dopant fluctuation, RDF (from device Vt adjust implant)
•Metal line thickness variation (from variations in layout density, from the CMP polishing process)
•Via resistance variation (due to variation in barrier metal thickness filling the damascene trench + via)
•Gate line edge roughness, LER (localized gate channel variation)

Additional Sources of Variation @ 20nm
•Double patterning A/B mask misalignment, resulting in extraction variation between adjacent lines
•Much stronger focus on “preferred orientation” segments — “wrong-way” segments have a much greater litho variation, due to source-mask optimization litho data correction
•Introduction of “local MEOL interconnect” for active + gate contacts introduces new source of width/thickness metal variation — the MEOL is a large contributor to the gate-to-source and gate-to-drain coupling capacitances

Additional Sources of Variation @ 16nm
•FinFET-related variations… fin height tolerances, fin thickness tolerances, fin profile variation
•Relative magnitude of gate LER is larger
Fin sidewall roughness is a new phenomenon

Additional Sources of Variation @ 10nm?
•Triple- or quad-patterning –> mask mis-registration goes up… greater extraction variation
•Very restrictive layout design rules — e.g., NO wrong-way segments on lower metal layers… as a result, some variation could be mitigated?
•Metal line and via resistance tolerances go up… narrower metals imply a greater % of the damascene volume will be the barrier layers… greater % variation?
•Metal gate “grain boundary effects” (MGG) more prevalent… the grain size of the metal gate material is approaching Lgate… higher % variation in Rgate?
•New metal gate workfunction interfaces for device Vt’s…?

You can sign-up for the DAC tutorial here: http://www.dac.com/dac+2013+registration.aspx, or sign-up for a Solido software demo here: http://www.solidodesign.com/page/dac-2013-demo-signup/

lang: en_US