Sigrity Focuses on LPDDR4 Compliance Analysis in 2015 Release

It was back in July of 2012 that the acquisition of Sigrity by Cadence was announced. Although Cadence is a dominant player in both IC and board layout tools, they did not have an electromagnetic (EM) signal integrity solution in their portfolio. This acquisition marks a turning point for the EM/SI sector – tight integration into the design flow is now exceedingly important for designers. As always there is a lot of anticipation to see how things go after a smaller technology company is brought in under the wing of a larger player.

Cadence is announcing the features in the new 2015 release of Sigrity at DesignCon this week. This is an ideal time and place for the announcement. DesignCon is a leading event in the board design space. The tag line for DesignCon is “where the chip meets the board”. With that in mind, the main features of the Sigrity 2015 release are right on target. Of the things intheir press release, the one that jumps out is added support for analysis and qualification of designs using the newLPDDR4 high-speed low-power memory interface standard.

The driver for this is the growth of mobile devices – more data and more graphics. According to a presentation at Mobile Forum 2013 by Samsung’s JungYong Choi, data traffic on PCs will grow by only 2X from 2012 to 2017, but smartphone data traffic will grow 8X in the same timeframe. Concurrently, higher resolution displays on mobile devices are also driving bandwidth. UHD needs 9X the bandwidth than HD does.

The JEDEC specification for LPDDR4 came out in August of 2014. Not only is it a faster interface standard, but it uses less power. Power is reduced by lowering the operating voltage from 1.2V in LPDDR3 to 1.1V in LPDDR4, Significant power is also saved by using Low Voltage Swing Terminated Logic. This uses a signaling voltage of around 400mV, 50% lower than the previous LPDDR3. Transmitting a ‘0’ requires almost no current. To save even more power DBI is used to invert the data bits when a byte has more ‘1’s than ‘0’s. Overall LPDDR4 is said to use 40% less power than LPDDR3.

LPDDR4 runs at 3.2B transfers per second; at the bus level that translates to a bandwidth of 25.6GB/s (2ch). The bus is divided into 2 parallel 16 bit buses with their own clocking to help improve signal line layout and avoid skew issues.

With low swing voltage and higher operating frequency comes the need for added diligence on interconnect to memory chips. Signal traces need to be analyzed to ensure that they do not contribute to excessive bit error rates. According to Brad Griffin, Product Marketing Director at Cadence, trace geometry and ground plane structure affects signal integrity and needs to be modeled and simulated to understand how the whole system will operate. Also ground bounce and power rail integrity will have a dramatic effect on LPDDR4 compliance.

Sigrity 2015 not only provides modeling for board and package interconnect, but can simulate the system using its power aware system signal integrity feature to ensure that the bit error rate complies with the specification. Sigrity ties into package level simulation and up through chip level models that can be generated in the Cadence suite.

Looking at things from a system perspective, it seems that Cadence is well positioned to leverage its entire flow to help validate and qualify designs from on-chip all the way to the board and system level. After all, things will only get more complicated. The next revision of the LPDDR4 spec will go from the present 3200 MT/s to 4266 MT/s, a much higher transfer rate. Griffin expects channel equalization to become a necessity before long. If so, this will add the requirement to model equalization algorithmically to perform end to end qualification.

I look forward to visiting the Cadence booth at DesignCon this week to learn more about Sigrity 2015.