Using Cadence PVS for Signoff at TowerJazz

TowerJazzis a specialty foundry that provides IC manufacturing into several markets, like: RF, high-performance analog, power, imaging, consumer, automotive, medical, industrial and aerospace/defense. In June there was a presentation from Ofer Tamir of TowerJazz at DACin the Cadence theatre, so I had a chance this week to learn about how they use the Physical Verification System (PVS) from Cadence. Other EDA vendors offering competitive tools in this space include: Mentor, Synopsys and Tanner EDA.

TowerJazz is a publicly traded company and we’ve seen the stock price increase some 75% this year, so that’s keeping the shareholders quite happy:

You’ll find fabs from TowerJazz in Israel, California and Japan. They even has a 12″ fab processing 40nm chips. Their Process Development Kits (PDKs) are filled with useful features, libraries and models for AMS design engineers:

The Cadence PVS has much more than just Design Rule Checks (DRC) and Layout Versus Schematic (LVS) tools because for signoff you need to handle more effects:

Engineers at TowerJazz create all of the files that IC designers will need to run each of the Cadence PVS tools. The PVS runset is written in the Physical Verification Language (PVL) for tools that perform: DRC, LVS, ERC and Fill. Users of the older Assura-QRC flow will find the PVS-QRC flow quite similar to run. Since the Calibre tool from Mentor is so entrenched, there’s a utility to compare DRC results between PVS and Calibre.

Related – InDesign DFM Signoff for 14 nm FinFET Designs

The PVS decks supported by TowerJazz include 180 nm to 130 nm nodes:

IC designers run the Cadence PVS tools like DRC using the PDK from TowerJazz on their layouts and get feedback as both text and location for each DRC error.

Related – Cadence Mixed Signal Technology Forum

Likewise, when running the LVS tool you can see and debug each mismatch both in text and graphically by cross-probing:

Extracting a parasitic netlist from layout is done with the QRC tool:

Using this QRC created netlist in a SPICE circuit simulator is the flow to get most accurate timing and power values for custom and AMS designs.

Related – How ST Designs with Layout Dependent Effects (LDE)

To enforce reliability rules for detecting Electro Static Discharge (ESD) issues there’s a tool called Programmable Electrical Rule Checker (PERC):

PERC tool results are similar to DRC or LVS by pin-pointing in the layout and schematic any technology-specific ESD issues.

Very large IC layout databases can be efficiently browsed with the PVS QuickView during error browsing and debugging steps.

Within TowerJazz they are doing design signoff with both Calibre and Cadence PVS tools. Users of Cadence Assura should consider migrating and adopting the PVS tools now.

View the complete 16 minute video online, and there is no registration required to view it.