Chiplets and Cadence at #62DAC

Using chiplets is an emerging trend well-covered at #62DAC and they even had a dedicated Chiplet Pavilion, so I checked out the presentation from Dan Slocombe, Design Engineering Architect in the Compute Solutions Group at Cadence. In a short 20 minutes Dan managed to cover a lot of ground, so this blog will summarize the key  points.

The need for IC design automation and chiplet automation is driven by the steady growth in the number of 5nm, 3nm and smaller nodes along with the goal of mixing and matching them as part of heterogeneous package-level, multi-die systems. Overcoming manual design challenges requires automation for: preventing stale documentation, reducing the number of human errors, abstracting low-level implementation details, preventing duplication of information sources, handling the proliferation of IPblocks used, having an automated verification strategy to reduce the number of time-consuming verification cycles, and minimizing development times.

At Cadence they are using an internal automation flow “SoC Cockpit” to meet these SoC challenges through:

• Capturing system-level specifications
• Using Cadence IP and partner IP libraries
• Configuration of IP library components
• Taking feedback from downstream flows
• Automating verification with simulation, emulation and virtual platforms
• Providing customer chiplet platforms and reference software

This approach aims to improve design efficiency from an executable spec through GDS II production. Here’s the basic correct-by-construction automation flow, where the specification is an executable spec; construction is the RTL with floor planning and database; software framework is the reference framework and drivers; design collateral is the testbenches, emulation and models; physical design encompasses RTL to GDS.

Design intent captured includes many details:

• Functional specification
• Top-level pinout
• I/O cell selection
• Pin multiplexing
• Clock tree definition
• Reset tree definition
• Voltage domain definitions
• Power domain definitions
• System maps
• Infrastructure and IP definitions

The SoC Cockpit flowchart encompasses multiple file formats and transformations.

Zooming into the SoC Builder there is SoCGen which starts with an executable spec, creates intermediate files, then finally passes the data to IPGen to create instances of IP. AI agents can be used to select which IP blocks meet the specifications. There are both built-in generators for Verilog RTL and plugin generators to work with a variety of formats: IP-XACT, SDC/UPS/USF, virtual platform, testbench, C/C++ header files.

Users work with a front-end GUI to guide through the specification capture process, enforcing the correct-by-construction approach. Cadence has been able to create this automated flow by harnessing their own tools and IP, like:

Front End 
Conformal Technologies
Jasper Apps
Joules RTL Solutions
Cadence Modus DFT Software Solution

Back End  
Genus Synthesis Solution
Innovus Implementation System
Cadence Cerebrus Intelligent Chip Explorer

Verification
Palladium Emulation
Protium FPGA-Based Prototyping Platform
Helium Virtual and Hybrid Studio
Xcelium Logic Simulator
Verisium AI-Driven Verification Platform
Perspec System Verifier

IP
Tensilica Processors
System IP, Partner IP
Interface IP – UCIe, PCIe
Memory – DDR, LPDDR, Flash

Summary

Cadence has adopted industry standards, including UCIe , Arm’s Chiplet System Architecture (CSA) and AMBA C2C protocols to ensure systems are built based on known standards. With the SoC Cockpit, the new automation features bring together architecture, design and implementation tasks resulting in faster availability of correct by construction designs. This automation reduces time to market and engineering efforts.

Partner with Cadence to help you realize your chiplet and SoC ambitions.

Related Blogs

• Cadence at the 2025 Design Automation Conference #62DAC
• Embracing the Chiplet Journey: The Shift to Chiplet-Based Architectures
• Accelerating Automotive SoC Design with Chiplets
• Cadence® Janus™ Network-on-Chip (NoC)
• Intel and Cadence Collaborate to Advance the All-Important UCIe Standard