How to Optimize Analog IPs for High-end SoCs?

Gone are the days when analog design had its sweet space on a single chip. However, it’s the main driver in this new electronic world which is geared by Internet-of-Things, wireless, mobile, remote control and so on. How does an electronic device sense a touch by human, motion, temperature, sound etc.? It’s the analog circuitry embedded into the SoC of your electronic device that connects the environment with the device. Quality, accuracy and speed of that sense matters very significantly, otherwise that electronic device will become a nuisance to you. Now you can very well imagine how complex and costly it would be to design a robust high-speed analog IP which can sit (without being disturbed by neighbouring noise) into the complex limited space, high performance, multiple functionality SoC of today. Typically, high performance data converters (between analog and digital), voltage regulators, sensors, clocks etc. are very common in demand.

The design can be better handled by looking at each issue objectively and focusing on important criteria to be met under particular circumstances. So, what are the key criteria to look at?

Sampling Rate – Faster sampling of data in a data converter achieves higher accuracy in rendition of analog signals. According to Nyquist theorem, to generate an accurate reproduction of an analog signal in digital form, the sampling rate should be higher than twice the highest frequency of the signal. However, there is cost involved in faster sampling; it requires higher bandwidth, more power consumption and challenge in synchronizing samples of each bit. Appropriate trade-off must be done depending on application area. The graph below summarizes typical levels of sampling rates and resolution for different applications.

Bit Resolution – This determines the accuracy of representation of analog signal into digital. A higher bit resolution produces analog signal more accurately into digital. A designer in this case can determine bit resolution based on how accurately a signal needs to be represented. For example, an audio device will need higher bit resolution as the voice needs clarity, whereas a thermal sensor in water temperature or air conditioner does not need that high resolution. The table below provides optimal ranges of sampling rate and resolution for various applications.

Noise Ratio – Noise reduces the accuracy of data conversion. Generally it is said that analog components are victims of digital aggressors in the semiconductor design. Care must be taken in placing the analog and digital components appropriately to keep SNR (Signal-to-Noise Ratio) under tolerable limits, even with possible margins by increasing bit resolution or sampling rate. Again, it depends on the type of appliance; an audio or wireless device is extremely sensitive to noise compared to a temperature sensor.

ENOB (Effective Number of Bits) – This reflects the actual performance of data conversion. Due to noise and distortion of signal, it’s not possible to get an ENOB as high as the number of bits in an ADC (analog-to-digital converter). An 11-bit ADC with an ENOB of 10.5 is considered to be well optimized and more effective design than a 12-bit ADC with an ENOB of 10. And hence it’s important that the system requirement are well understood before designing.

Power – This is a major concern for all designs, especially with analog circuits getting into mobile applications. It’s DAC (digital-to-analog converter) that needs more power to drive higher amplitude signal. The challenge is to achieve high amplitude without sacrificing power.

While considering all these challenges and the need for careful evaluation of options, what we did not talk about is the time taken to design such analog IPs. It takes considerable time and that adds into overall design cycle time impacting on time-to-market in a highly competitive semiconductor industry. It’s highly desirable to choose best IPs already optimized with performance and standardized on different criteria and integrate them into SoCs. Cadence offers a broad portfolio of more than 250 silicon-proven analog IPs that include 7-bit 3GSPS dual ADC and DAC, 11-bit 1.5GSPS dual ADC and 12-bit 2GSPS dual DAC which support 28nm designs and provide a conversion rate up to 10X faster compared to competing solutions.

Bob Salem and Kevin Yee from Cadence have very elaborately described these challenges of high-speed analog IPs in their whitepaperposted at Cadence website. It’s an interesting read.

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