Breker Verification Systems at the 2025 Design Automation Conference #62DAC

Breker Verification Systems Plans Demonstrations of its Complete Synthesis and SystemVIP Library and Solutions Portfolio

Attendees who step into the Breker Verification Systems booth during DAC (Booth #2520—second floor) will see demonstrations of its Trek Test Suite Synthesis and SystemVIP libraries and solutions portfolio.

They will learn about complex application processor projects across the SoC and RISC-V core verification stack including data center, automotive, AI accelerator and consumer device applications where Breker’s Trek Test Suite Synthesis and Cache Coherency SystemVIP are deployed.

Breker’s SystemVIP library with Test Suite Synthesis allow for enhance verification coverage while significantly reducing test development time for complex scenarios incorporates debug and coverage analysis and can be ported across simulation, emulation, prototyping, post-silicon and virtual platform environments.

SystemVIP includes prepackaged, automated, self-checking scenario verification libraries, while Test Suite Synthesis is AI-driven, offering high-coverage, corner case bug hunting, test content generation and abstract reusable portability across verification platforms.

Starting with randomized instruction generation and microarchitectural scenarios, SystemVIP includes unique tests that check all integrity levels ensuring the smooth application of the core into an SoC, regardless of architecture, and the evaluation of possible performance and power bottlenecks and functional issues.

The SystemVIP Scenario Library enables high-coverage test generation using AI planning algorithms, test cross combination and concurrent test scheduling. The scenario library includes tests for system coherency in multicore SoCs, Arm integration, RISC-V core integrity, power domain switching, hardware security access rules, automated packet generation and performance profiling.

Engineers developing complex RISC-V cores or leveraging them in their SoCs must take on new verification scenarios that require different techniques. Breker’s SystemVIP can be extended for custom RISC-V instructions to be fully incorporated into the complete test suite crossed with other tests and used for a variety of complex RISC-V core designs. Those include system coherency in multicore SoC integrity test sets, high-coverage core test, power domain switching, hardware security access rules and automated packet generation

The verification of processor cores that leverage the RISC-V Open Instruction Set Architecture (ISA) requires testing specialized, unique scenarios, making Breker’s RISC-V SystemVIP libraries ideal scenario platforms. The libraries use AI Planning Algorithms, cross-test multiplication and concurrent, multi-threaded scheduling to provide rigorous testing from randomized instructions to unique coherency, paging and other complex system integration validation.

Semiwiki readers are invited to arrange demonstrations or private meetings by sending email to info@brekersystems.com or stopping by Booth #2520.

DAC Registration is Open

About Breker Verification Systems

Breker Verification Systems solves complex semiconductor challenges across the functional verification process from streamlining UVM-based testbench composition to execution for IP block verification, significantly enhancing SoC integration and firmware verification with automated solutions that provide test content portability and reuse. Breker solutions easily layer into existing environments and operate across simulation, emulation and prototyping, and post-silicon execution platforms.

Its Trek family is production-proven at leading semiconductor companies worldwide and enables design managers and verification engineers to realize measurable productivity gains, speed coverage closure and easy verification knowledge reuse. As a leader in the development of the Accellera Portable Stimulus Standard (PSS), privately held Breker has a reputation for dramatically reducing verification schedules in advanced development environments. Case studies that feature Altera (now Intel), Analog Devices, Broadcom, IBM and other companies leveraging Breker’s solutions are available on the Breker website.

Engage with Breker at:
Website: www.brekersystems.com
Twitter: @BrekerSystems
LinkedIn: https://www.linkedin.com/company/breker-verification-systems/
Facebook: https://www.facebook.com/BrekerSystems/

DAC registration is open.

Also Read:

RISC-V Virtualization and the Complexity of MMUs

How Breker is Helping to Solve the RISC-V Certification Problem

Breker Brings RISC-V Verification to the Next Level #61DAC