A Comprehensive Power Optimization Solution

In an electronic world driven by smaller devices packed with larger functions, power becomes a critical factor to manage. With power consumption leading to heat dissipation issues, reliability of the device can be affected, if not controlled or the device not cooled. Moreover, for mobile devices such as smartphones or tablets that run on battery, low power consumption is essential. For a holistic solution to the power problem, it is important that this is addressed at the source, i.e. the design stage. For SoCs with robust power optimized designs, comprehensive EDA tools are needed that can accurately measure and estimate power requirements, reduce power by utilizing various techniques, and verify the power at every stage of the design starting from RTL to the physical netlist. The RTL stage coming early enough in the design process and being detailed enough; it is the sweet spot that provides the largest avenue for power reduction and optimization.

Atrenta’sSpyGlass Powerprovides a complete solution for power optimization that analyzes and reduces power, verifies the original RTL against the new modified RTL, and ensures the design is compliant with the power intent, post-synthesis and post-layout. The power reduction is done by utilizing several approaches including power exploration at the SoC architecture level, manually fixing critical blocks with tool guidance, and automatic power optimization of non-critical blocks.

Figure 1: Power optimization flow

The SpyGlass Power optimization flow works interactively between power estimation, reduction and verification. The power estimation can be done with user specified inputs without vectors, or with simulation/emulation data in VCD, FSDB, or SAIF files. Different modes can be used such as average, cycle-based, or hybrid, depending on the requirement; for example, in cases of memories, cycle-accurate monitors are applied by default, even in average mode. For predictable accuracy, calibration is done against a reference netlist, and a correlation toolbox is used for models of capacitance, clock tree, and so on. The beauty of the SpyGlass Power solution is that with physical-aware power estimation, it can even skip the calibration and correlation step, while still producing the same level of accuracy by leveraging timing and physical optimization engines. This is a solution that will be introduced soon in SpyGlass Power, providing enhanced local fidelity and allowing trade-off analysis between different physical prototypes.

Along with power estimation, SpyGlass Power also performs power profiling and provides power efficiency metrics that include information such as ‘Clock Gating Ratio’, ‘Intrinsic Clock Gating Efficiency’, ‘Incremental Clock Gating Efficiency’, and ‘Register Output Activity Density’. Designers can analyze this data and make informed decisions to either accept particular clock gating and register structure, or modify them manually to increase power efficiency.

Figure 2: Power Explorer

Within the tool, there is a versatile Power Explorer,which is a rich GUI that works as a central cockpit for top-down power methodology and efficient power reporting, analysis, and suggested next steps for improvement. The master view with hierarchical instances contains information about design objects such as registers, combinational logic, power profile numbers, annotations, and so on. The report can be easily customized as required and presented in different matrix forms. Similarly the slave or secondary views contain information about registers, memories, clocks, micro-architectures, and opportunities for power saving.

SpyGlass Power uses formal sequential analysis techniques to identify ‘Enables’ beyond synthesis tools for sequential power reduction. While introducing registers for Enables, it leverages SpyGlass CDC to keep the design CDC-safe. Similarly memory power reduction is achieved by using techniques such as ‘redundant access removal’ and automatic activation of ‘light sleep mode’.

Figure 3: Activity Trigger Detection

There is a very effective and useful technique called ‘Activity Trigger Detection’ that is used to identify events that can up-surge or down-surge activities and turn parts of the design ON or OFF. The signals that are root causes of such changes are identified with a combination of statistical, structural, and formal approaches, and the events can be combined to gate a particular block or even power-gate it.

Figure 4: Examples of Power Guidance rules

SpyGlass Power provides power guidance for micro-architectural improvements such as ‘FIFO optimization’, ‘counter gating’, ‘glitch detection and removal’, and so on. It works with or without vectors. ‘Power lint’ can be used to improve RTL without vectors. With vectors, the power guidance also provides information about specific modifications with their expected power gains.

As part of power verification, SpyGlass Power has an independent Signoff Verification Solution that supports UPF 2.0/2.1 with a single tool for RTL, post-synthesis netlist, and post-layout netlist verification. The power intent browser cleanly represents power at every block or IP level without design clutter and with cross-probing features. The non-instrumented RTL is verified with power intent “lint” checks and power intent consistency checks. On instrumented RTL or netlist designs where low power elements such as isolation cells or level shifters are inserted, the checks also flag if the implementation is improper. The signoff power verification on post-synthesis netlist ensures correct implementation of power elements, while on post-layout netlist the tool also ensures all supply connections are correct via ERC (Electrical Rule Checks).

SpyGlass Power also has a powerful debug environment with several features such as power annotation on schematics, click on port to see isolation, retention or level-shifting strategy, and cross-links between violation messages, power intent browser, schematics, design files, etc. Additionally, some functional checks can be done through formal power verification based on design functionality and power intent.

SpyGlass Power has seamless integration of all these technologies within the SpyGlass platform and provides a powerful comprehensive solution for power estimation, analysis, optimization and verification. This solution for power optimization and verification has been adopted by many leading semiconductor companies.

A very detailed description with several examples about SpyGlass Power solutionwas presented in a webinarby Guillaume Boillet, Sr. Technical Marketing Manager at Atrenta. The webinar can be attended on-line after a one-step free registration on the Atrenta website here.