UVM Debugging Made Easy & Productive in Questa

As design complexity and size is increasing, SoC verification has become one of the most difficult and time consuming tasks in the design closure.UVM (Universal Verification Methodology, an accellera initiative) is one of the best verification methodologies that support common language, coherent strategy, clarity and transparency and most importantly, provide easy-to-use APIs. Today, UVM is a very popular SoC verification methodology. Among various tasks associated with verification such as test planning, test bench preparation, test creation, test run, and debugging, most of the time is spent in debugging. UVM provides freedom to use its APIs in best possible ways in any user environment such that the verification and debugging can be optimized according to the environment.

Mentor’sQuesta Verification Platform has integrated UVM that provides a powerful and productive environment for debugging designs. The Questa_UVM package is just add-on SystemVerilog package which enables better UVM debug for Questa users. Any UVM kit is pre-compiled in Questa and does not require any kind of instrumentation. Although UVM source code is also provided along with Questa, it is recommended to use pre-compiled version for easy use of the built-in Questa UVM debug.

vsim –uvmcontrol=all
An ‘uvmcontrol’ switch with various options can be used with ‘vsim’ simulator command. It’s recommended to use ‘all’ option that includes all UVM-aware functionality and debug options except ‘disable’ and ‘verbose’. There are other options to control visibility into debugging by setting only desired blocks in the hierarchy to be visible and hence optimize the overall debug process. The visibility can be enabled selectively in the RTL as well.

Questa uses a specific nomenclature to define various class types and their unique instances. With SystemVerilog classes, Questa provides software-like debug views of class tree and class graph. It uses OOP (Object Oriented Programming) methodology for inheritance relationships. A class tree is shown in the above picture where classes, their extensions, methods, properties etc. can be seen in a hierarchical view.

Similarly all SystemVerilog classes can be seen graphically. Any particular class can be zoomed in to see methods and properties associated with it.

Any function call stack can be seen in a ‘call stack window’ to analyze the depth of function calls. Several commands are provided which can be executed directly from command line or from simulator command line. For example, ‘call’ can be used to call any UVM SV function; ‘findregisters, fr’ can be used to find HDL registers for a UVM register model; ‘findsequences, fs’ can be used to find currently active sequences; and so on. There is a very useful command called ‘find insource’ that searches through only compiled code to find the given matching string. The returned text is hyperlinked that can be clicked to go straight to the source code.

Questa has methods to aggregate data into a single entity for viewing in the ‘wave window’. These entities are called transaction streams (blue stars in the above picture). The transaction streams are created automatically in UVM. Questa system calls allow flexibility in defining these transaction streams. To record a transaction stream, begin_tr() and end_tr() functions are called in drivers and monitors which automatically call do_record(). The do_record() function has been added in Questa as part of UVM debug features.

The transactions can be viewed in detail and analyzed in the ‘wave window’. Any particular item can be clicked and seen in more detail in a pop-up window.

A detailed view of the advanced UVM debugging can be seen in an on-line webinarposted on Mentor website. Tom Fitzpatrick, Verification Evangelist at Mentor, has described strategies for debugging UVM-based test benches in Questa environment in great detail. He also demonstrated live debugging with an example test bench that shows the real power of the Questa Verification Platform along with UVM.

This is an excellent platform that enhances class-based SystemVerilog debugging for UVM. The performance is optimized while preserving visibility in debugging design blocks. The UVM methods can be called directly from command line that enhances verification engineer’s productivity.