Tag: sequence

Portable Stimulus Tutorial: “Efficient Portable Programming Sequence Development with PSS”

Portable Stimulus Tutorial: “Efficient Portable Programming Sequence Development with PSS”
by Admin on 02-20-2024 at 3:55 pm

Accellera at DVCon U.S. 2024

Efficient Portable Programming – Sequence Development with PSS

Bringing an SoC-level system out of reset into an operational state involves configuring the component subsystems and IPs by properly programming hundreds or thousands of IP registers. Running behavior involves programming… Read More

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Never Imagined So Easy Class-based Testbench Debugging

Never Imagined So Easy Class-based Testbench Debugging
by Pawan Fangaria on 08-09-2015 at 7:00 am
Categories: EDA, Siemens EDA

When it comes to debugging a design testbench organized in object-oriented style with objects, component hierarchies, macros, transactions and so on, it becomes an onerous, tasteless, and thankless task for RTL verification engineers who generally lag in software expertise. Moreover, class-based debugging tools have lagged… Read More

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UVM Debugging Made Easy & Productive in Questa

UVM Debugging Made Easy & Productive in Questa
by Pawan Fangaria on 02-11-2015 at 2:00 pm
Categories: EDA

As design complexity and size is increasing, SoC verification has become one of the most difficult and time consuming tasks in the design closure.UVM (Universal Verification Methodology, an accellera initiative) is one of the best verification methodologies that support common language, coherent strategy, clarity and transparency… Read More