Moving Beyond RTL at #62DAC

Hardware designers have been using RTL and hardware description languages since the 1980s, yet many attempts at moving beyond RTL have tried to gain a foothold. At the #62DAC event I spent some time with Mike Fingeroff, the Chief High-Level Synthesis Technologist to understand what his company Rise Design Automation is up to. Mike has two decades of experience in High Level Synthesis (HLS) and even authored a book in 2010 on HLS.

One major theme at DAC this year was using GenAI to create RTL faster. At RISE they support a methodology using several higher-level languages like SystemVerilog, C++ or SystemC. Verilog designers gravitate towards using SystemVerilog with loose timing for control flow designs, while C++ is an appropriate language for dataflow designs. Mike thinks that you should use the best language for each block, then mix abstractions as needed.

All of the popular EDA simulators support multiple languages for design descriptions spanning from RTL to transaction level. Many tier-one companies have proven that HLS flows are more productive than RTL: Google, NVIDIA, Qualcomm. The new challenges are providing a complete tool chain for HLS that use AI agents, instead of requiring experts to run the tools.

With RISE there are AI advisors and agents to help you generate high-level code using LLMs that already understand high-level coding from Python and C repositories. Their AI works with engineers to create the code easily by using chat prompts. Traditional LLMs are being used either on-premise or in the cloud, your choice, and they are pre-trained for you.

An LLM doesn’t really know HW design, so they had to show them how to make HW from C++ code. They have an Agent Orchestrator that calls the RISE tools, views the results, and continues to iterate to explore the design space. This iteration loop can also contain logic synthesis and P&R tools as well.

Rise.ai Adviser is a generative AI advisor aimed at high-level design with natural language input, creating designs in SystemVerilog, SystemC and C++. Test benches are created in both C++ and UVM. You can analyze your design then optimize for area, power or speed. This all runs on a local processor or something larger if you really want to. During design exploration you can call your own tools, like VCS for power numbers, or Open ROAD tools for synthesis and P&R.

Verification speed ups with higher abstraction levels range from 100X to 1,000X faster. RISE verification has automatic channel capture for waveforms, automatic high-level to RTL comparisons, and utilities for sub-system assembly and verification testbenches.

Summary

RISE Design Automation did create a buzz at DAC this year, because their message was something that RTL designers want – becoming more productive by raising the design and verification abstractions, using faster toolchains and benefitting from generative AI integration. You can learn more about RISE by visiting their website and then think about starting an evaluation to produce better design and verification results from your team.

Related Blogs

• Generative AI Comes to High-Level Design
• Upcoming Webinar: Accelerating Semiconductor Design with Generative AI and High-Level Abstraction
• An Imaginative Approach to AI-based Design
• CEO Interview: Badru Agarwala of Rise Design Automation