Earlier I blogged about IC and ASIC functional verification, so today it’s time to round that out with the state of FPGA functional verification. The Wilson Research Group has been compiling an FPGA report every two years since 2018, so this marks the third time they’ve focused on this design segment. At $5.8 billion… Read More
Tag: python
The State of FPGA Functional Verification
The State of IC and ASIC Functional Verification
Way back in 2002 there was a study from Collett International Research on functional verification, and since 2010 the Wilson Research Group has continued that same kind of study with a new report every two years. What attracts me to this report is that it doesn’t just look at the installed base of one EDA vendor, instead it looks… Read More
Ansys 2023 R1: Ansys PyFluent What’s New
Ansys 2023 R1 PyFluent updates include a new embedded PyConsole, centralized python journaling, and auto complete and Fluent commands. Don’t miss this webinar to learn about these exciting new PyFluent updates.
TIME:
MARCH 7, 2023
10 AM EST
About this Webinar
We’ll highlight the significant advancements in PyFluent, which
Webinar: Boost your Ansys Digital Twin with PyAnsys: Learn How
Join this webinar to get introduced to the latest PyAnsys package, “PyTwin,” giving easy access to the power of Ansys Digital Twins Runtimes through Python APIs.
TIME:
FEBRUARY 14, 2023
11 AM EST / 4 PM GMT / 9:30 PM IST
About this Webinar
Ansys Digital Twins workflows enable users to build, validate and deploy connected Digital Twins
DVClub Europe
DVClub Europe: Make Verification Fun Again with Python and cocotb
Make Verification Fun Again with Python and cocotb
cocotb is an open source coroutine-based cosimulation testbench environment for verifying VHDL and SystemVerilog RTL using Python. cocotb connects a testbench written in Python with almost all industry-standard… Read More
Live Webinar: Engineering best practices for Python-based testbenches with cocotb (US)
Philipp Wagner, Co-maintainer of cocotb and Hardware/Software Engineer at lowRISC
Abstract:
Writing code is easy. Reading code is hard. Maintaining code is hard. Writing “good” code is hard. So what’s “good code”? Don’t despair: the software engineering community has come up with
Python in Verification. Veriest MeetUp
Veriest held a recent meetup on a topic that has always made me curious – use of Python in verification. The event, moderated by Dusica Glisic (technical marketing manager at Veriest), started with an intro from Moshe Zalcberg (CEO of Veriest) and talks by Avidan Efody (Apple verification) and Tamás Kállay (Team leader, Veriest).… Read More
Happy Birthday UVM! A Very Grown-Up 10-Year-Old
.The UVM standard was first released by Accellera 10 years ago this month and is now by far the leading methodology for functionally verifying logic designs, especially at the block level. As I write, DVCon fast approaches so I talked to Tom Fitzpatrick, Verification Technologist at Siemens EDA (Mentor Graphics) for a perspective.… Read More
High Frequency Trading and EDA
Pop quiz – name an event at which an EDA vendor would be unlikely to exhibit. How about The Trading Show in Chicago, later this month? That’s trading as in markets, high-frequency trading, blockchain and all that other trading-centric financial technology. This is another market, like cloud, where performance is everything and… Read More