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WP_Term Object
    [term_id] => 157
    [name] => EDA
    [slug] => eda
    [term_group] => 0
    [term_taxonomy_id] => 157
    [taxonomy] => category
    [description] => Electronic Design Automation
    [parent] => 0
    [count] => 3902
    [filter] => raw
    [cat_ID] => 157
    [category_count] => 3902
    [category_description] => Electronic Design Automation
    [cat_name] => EDA
    [category_nicename] => eda
    [category_parent] => 0

Active Power Management in UPF Using SPICE, VHDL-AMS or Verilog-AMS

Active Power Management in UPF Using SPICE, VHDL-AMS or Verilog-AMS
by Daniel Payne on 05-31-2014 at 9:20 pm

My former co-worker, Kenneth Bakalar at Mentor Graphics is an expert in AMS modeling languages and UPFmethodology, so he recently teamed up with Eric Jeandeau to author an interesting white paper: Interpreting UPF for a Mixed-Signal Design Under Test. This white paper is based on a presentation made at DVCon earlier this year. The basic idea presented in this 16 page paper is that modern SoCs use lots of power-management techniques to power-down and power-up blocks in the quest to conserve power, and that you should be able to model the effects of this in a UPF-based simulation flow.

You start out with a digital design and it’s UPF file. Next, you will swap out a digital block for an AMS model where the new electrical ports correspond directly to the previous digital block ports. The AMS model contains extra electrical ports that will supply power to the analog sub-circuit within the model. Each analog power supply connected to the ports will get synchronized with the actual power state of the UPF power domain for this instance.

As digital signals are connected to electrical nets, it’s required that a signal connect element be inserted to enable communication between digital and analog realms. Here’s a diagram showing a signal connect element:

General model of a power sensitive, bidirectional signal connect element

Connect Elements

Coding examples in VHDL-AMS for electrical to real, and electrical to logic are shown below. If the input analog voltage changes by as much as the tt parameter (1mV), then a new digital value is driven on outp. There’s also a check on the power state, and if either power net is OFF, then the output is driven to voff.

VHDL-AMS entity for an electrical to real (A2D) connect element

VHDL-AMS architecture for an electrical to logic (A2D) connect element

Connect elements are also written for a logical to electrical (D2A).

When connecting UPF power to analog pins we really want the power/ground pair to be dynamically responsive to the controls described by UPF. The technical solution to this is inserting a power to electrical element (P2E), and here’s the code example written in VHDL-AMS:

VHDL-AMS model for a P2E

This P2E model will convert digital input upfin of supply_net_type into an analog voltage, and upfin indicates if the digital power port is powered up or down. The power state control both the voltage and impedance of the branch from vdd to vds, which is then used by the analog blocks. The rise and fall times are also coded.

The converse of P2E is called E2P, and this connect element is interposed between electrical to power.

The good news is that the engineers at Mentor have implemented all of these connect elements and supported methodology into the Questa ADMS mixed-signal simulator. An example of how connect elements are used is shown in a mixed-signal design under test, called YDUT:

Example design under test with a testbench

AOT_TEST is the top-level and is defined in SPICE, while the XTOP subcircuit is also in SPICE, finally YDUT is the digital Verilog design under test. Verilog instance YSTIM controls all four of the UPF power domains:

The timing for the power domains is coded in the testbench stimulus, and here’s the timing diagram:

Multiple tests were written to control each power domain, and here we see that power domain pd_top turns on at 100 us, and two outputs then become active:


It is possible in a UPF design to model the power characteristics by adding SPICE, VHDL-AMS or Verilog-AMS models. Mentor’s Questa ADMS simulator has been extended with two new methods:


  • Providing UPF-controlled, SPICE-level power to AMS instances as needed
  • Defining signal connect elements that are aware of power state of each UPF power domain.

    If you’re visiting DAC this week, then stop by booth #1733 and ask about Questa ADMS.

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