SoC Design Closure Just Got Smarter

Near the end of any large SoC design project, the RTL code is nearly finished, floorplanning has been done, place and route has a first-pass, static timing has started, but the timing and power goals aren’t met. So, iteration loops continue on blocks and full-chip for weeks or even months. It could take a design team 5-7 days per iteration – not knowing how much time per iteration, and not really knowing how many iterations will reach closure of their design goals. Clearly, not a fun process to be caught in.

The clever R&D engineers at Cadence have taken action to deliver some relief for reaching design closure by creating a full-chip closure flow, and it uses an automated approach that is massively distributed, delivering both optimization and signoff. I talked with Brandon Bautz, senior group director, product management in the Digital & Signoff Group at Cadence, to learn about their newest EDA announcement. The new offering is called the Cadence Certus Closure Solution, and it has a shared engine with the Cadence place and route tool, the Innovus Implementation System, and the Static Timing Analysis (STA) tool, the Tempus Timing Signoff Solution. Here’s how the Cadence Certus Closure Solution works with STA (Tempus), place & route (Innovus), fill (Pegasus Verfication System) and extraction (Quantus Extraction Solution):

Reaching block-level closure is accomplished through using Tempus for STA along with Tempus ECO, controlled by the Cadence Certus Closure Solution. For full-chip and sub-system level closure, the Cadence Certus Closure Solution controls Tempus Signoff using either STA or distributed STA (DSTA). SemiWiki has written about how Cadence applied ML to chip optimization steps with the introduction of the Cadence Cerebrus Intelligent Chip Explorer last year, and this also works with the Cadence Certus Closure Solution.

As your SoC design size increases you really want an EDA tool that scales, so with the Cadence Certus Closure Solution you get a design closure flow that is distributed, and supports hierarchical optimization, ready to run in the cloud or your own data center to get results more quickly. When a change is made within a block, then the incremental signoff only needs to restore and replace the changed area.

Designers of 3D ICs will also benefit from the Cadence Certus Closure Solution, as it works with the Integrity 3D-IC platform, closing the timing on inter-die paths.

Certus Results

Two customer designs were run through the Cadence Certus Closure Solution, showing some impressive timing optimization and closure times that were gained overnight – not taking weeks and months.

N6 design

• 22M instances
• Cadence Certus Closure Solution Client Manager – 8 CPUs, 150GB
• Cadence Certus Closure Solution  Clients – 4 CPUs, 50GB

Timing optimization and closure, overnight, resulting in 10X improved TAT.

N16 design

• 140M instances
• Cadence Certus Closure Solution Client Manager – 4 CPUs, 200GB
• Cadence Certus Closure Solution  Clients – 8 CPUs, 600GB
• Timing optimization and closure – overnight results with
• 8X TAT improvement
• 9.7% power improvement for interface and 1.3% at a full-chip level

Even Renesas was quoted as seeing, “6X faster chip-level signoff closure turnaround times.”

If you have some STA and P&R experience, then learning the Cadence Certus Closure Solution  will be quick, as you can read the user guide and run through the examples, becoming proficient within just one day. The Cadence Certus Closure Solution works well on the largest SoC designs, and also on IP blocks with millions of cells. The approach in the Cadence Certus Closure Solution applies to all silicon technology: Planar, FinFET, Gate-All-Around.

Summary

Grunt work like manually trying to iterate EDA tool flows in reaching design closure on timing and power is expensive in both engineering costs and lost time to market. Cadence now offers new automation and optimization in the Cadence Certus Closure Solution by using a massively distributed flow that handles unlimited capacity. Engineering teams can expect to get overnight, concurrent full-chip optimization and signoff results.

This new automation area for Cadence looks promising, as it has the potential to save so much time and manual engineering effort.

Related Blogs and Podcasts

• Podcast EP112: How Cadence is Revolutionizing Full-Chip Signoff with Certus
• Using AI in EDA for Multidisciplinary Design Analysis and Optimization
• More Than Moore and Charting the Path Beyond 3nm
• Cadence Tempus Update Promises to Transform Timing Signoff User Experience
• Cerebrus, the ML-based Intelligent Chip Explorer from Cadence