Optimizing Prototype Debug

Optimizing Prototype Debug
by Bernard Murphy on 11-09-2016 at 7:00 am

In the spectrum of functional verification platforms – software-based simulation, emulation and FPGA-based Image Removedprototyping – it is generally agreed that while speed shoots up by orders of magnitude (going left to right) ease of debug drops as performance rises and setup time increases rapidly, from close to nothing… Read More


Mentor at DVCon – Visualize This

Mentor at DVCon – Visualize This
by Bernard Murphy on 03-10-2016 at 12:00 pm

Steve Bailey entertained us during lunch on Tuesday with a talk on debug and visualization in the Mentor Image Removedplatform. Steve is based in Colorado, so had to spend the first part of his talk gloating about their Super Bowl win, but I guess he deserves that.

On a more technical note, he showed us a familiar survey they had completed… Read More


Full Visibility in ASIC Prototypes at DAC

Full Visibility in ASIC Prototypes at DAC
by Daniel Payne on 06-24-2013 at 3:46 pm

ASIC prototyping from multiple vendors using FPGA boards was popular at DAC again this year in Austin, Texas. I stopped by the Tektronix booth for a few minutes to meet with Dave Orecchio to get an update.

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Dave Orecchio (right), TektronixRead More


SoC Optimization Using FPGA Prototyping

SoC Optimization Using FPGA Prototyping
by Daniel Payne on 05-18-2013 at 11:00 am

As an engineer I learn new concepts best by seeing a demonstration, in this case it was a demo of how to optimize SoC performance by using an ASIC prototyping debug process. SoC designers that use FPGAs to prototype their new ASIC often encounter debug issues, like:

  • Limited observability of internal nets required for debug, maybe
Read More

Tektronix at #50DAC

Tektronix at #50DAC
by Daniel Nenni on 05-13-2013 at 10:00 am

Image RemovedIf we grew up in similar eras you will know Tektronix as a company that manufactures test and measurement devices. Every lab I was in during high school and college had Tek oscilloscopes and logic analyzers. At #50DAC however, attendees that visit Tektronix will experience firsthand RTL simulation-level visibility… Read More


Accelerating Design Debug in an ASIC Prototype

Accelerating Design Debug in an ASIC Prototype
by Daniel Nenni on 04-30-2013 at 8:15 pm

ASIC prototyping in FPGAs is starting to trend on SemiWiki. As FPGA technology becomes more advanced customers tell me that the traditional debug tools are inadequate. Faced with the very restrictive debugging capabilities and very long synthesis/place/route times the debugging cycle in these prototype platforms are quite… Read More


Embedding 100K probes in FPGA-based prototypes

Embedding 100K probes in FPGA-based prototypes
by Don Dingee on 11-06-2012 at 8:15 pm

As RTL designs in FPGA-based ASIC prototypes get bigger and bigger, the visibility into what is happening inside the IP is dropping at a frightening rate. Where designers once had several hundred observation probes per million gates, those same several hundred probes – or fewer if deeper signal captures are needed – are now spread… Read More


Improving FPGA Prototype Debugging

Improving FPGA Prototype Debugging
by Daniel Payne on 10-30-2012 at 10:00 am

FPGA Prototyping is growing in popularity as a method to get an SoC design into hardware running at clock speeds up to 100MHz or so. One downside during traditional FPGA prototyping debug is the limited number of internal signals that you can observe while trying to chase down bugs in the hardware design in the presence of running … Read More