WP_Term Object
(
    [term_id] => 130
    [name] => Pulsic
    [slug] => pulsic
    [term_group] => 0
    [term_taxonomy_id] => 130
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 6
    [filter] => raw
    [cat_ID] => 130
    [category_count] => 6
    [category_description] => 
    [cat_name] => Pulsic
    [category_nicename] => pulsic
    [category_parent] => 157
)
            
pulsic semiwiki banner
WP_Term Object
(
    [term_id] => 130
    [name] => Pulsic
    [slug] => pulsic
    [term_group] => 0
    [term_taxonomy_id] => 130
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 6
    [filter] => raw
    [cat_ID] => 130
    [category_count] => 6
    [category_description] => 
    [cat_name] => Pulsic
    [category_nicename] => pulsic
    [category_parent] => 157
)

Analog IC Layout Automation Benefits

Analog IC Layout Automation Benefits
by Daniel Payne on 03-07-2022 at 10:00 am

I viewed a recent webinar from Paul Clewes of Pulsic, and the topic was Balancing Analog Layout Parasitics in MOSFET Differential Pairs. This topic interests me, because back in 1982 I wrote my first IC layout automation tool at Intel that automatically created 15% of a GPU chip layout called the 82786, then joined Silicon Compilers in 1986 where IC layout automation really was push-button for users. Historically the automation of digital layout blocks came first, as analog IC layout has many more requirements than digital and was just too difficult.

For a differential pair amplifier there are a number of specific requirements to ensure robust performance, like:

Differential Pair Schematic
Differential Pair Schematic
  • Matching transistor W and L values in amplifier
  • Interconnect parasitic balancing
  • Use of common centroid layout to reduce layout-dependent effects
  • Current mirror layout with smallest parasitic RC values

Analog IC Layout Automation

Paul showed how the Animate Preview plugin works inside of the Cadence Virtuoso environment, and that it automatically identifies schematic structures like current mirrors and differential pairs, then constrains the layout placement just like a skilled IC layout designer would do manually. You get to quickly see multiple layout scenarios within a minute or so, and each layout is already DRC clean by construction, saving you more time.

Animate Preview min
Example Analog Schematic

Clicking on the first automatically generated layout brings up the Animate Preview dialogs, showing windows for: Hierarchy, Schematic, Layout, Results and Constraints. The Layout window showed nine generated layout topographies. In the Results window there are analytics for each of the nine layouts, like aspect ratio, width, height and area. Every auto generated constraint from the Schematic is listed in the Constraints window.

Nine layout choices
Nine Layout Choices

Animate identified the differential pair from the schematic, and zooming into the schematic you can view the layout options for transistor layout like the number of layout rows used. Clicking anything in the schematic will cross-probe and highlight that device in the layout window.

Transistors M19 and M20 in the schematic define the differential pair, and the layout shows how these devices were placed in regular rows and columns known as a common centroid, which helps minimize process variations and also has matched spacings in both vertical and horizontal directions. Poly heads are defined in the same direction as part of the matching.

M19 and M20 min
M19 and M20, schematic and layout

To further refine this layout and improve the vertical matching, a new dummy row was added above and below devices M19 and M20 by selecting a menu option:

Dummy rows min
Dummy rows added

The metal routing details can also be viewed in Animate, along with viewing just Poly, Metal 1, Metal 2, Metal 3, Metal 4 and Metal 5 layers so that you can confirm that interconnect in the differential pair is identical and balanced. Routing to Source and Drain nodes were visually compared, and they were balanced.

Common centroid layout was also shown for the four current mirror devices: M8, M10, M11, M12. Routing between the current mirror and differential pair is also minimized and symmetrical, by design. Examining the routing between current mirror and differential pairs revealed that the metal layers were indeed symmetrical and identical.

Current Mirror min
Current Mirror Devices

The output of the differential pair connects to two more devices, and even the placement and routing of these devices is balanced. A constraint choice was changed from Base Analog to Mirrored Base Analog to show how you can control the symmetric layout for devices on the left-hand side (Red), and right-hand (Green) side. The butterfly layout choices can be seen below:

Mirrored Base Analog min
Mirrored Base Analog

Summary

In the old days of analog IC design the circuit designer drew the schematic and maybe added some annotations or notes for the layout designer, then threw the schematic over the wall. The layout designer read the annotations, made some placements and routing, then threw the layout back over the wall to the circuit designer. Finally, the circuit designer would examine the IC layout for symmetry and matching, and request refinements, creating a loop that had to iterate until matching constraints were met.

The new method from Pulsic enables a circuit designer to quickly create a balanced and symmetric layout in minutes, not days, all because of the inherent automation designed into Animate.

View the 29 minute archived webinar online.

Related Blogs

Share this post via:

Comments

There are no comments yet.

You must register or log in to view/post comments.