White Paper: A Closer Look at Aging on Clock Networks

We all know that designers work hard to reach design closure on SOC designs. However, what gets less attention from consumers is the effort that goes into ensuring that these chips will be fully operational and meeting timing specs over their projected lifetime. Of course, this is less important for chips used in devices with projected lifespans of a few years, such as cell phones. Yet, aging is a major issue for designs that go into applications that call for many years or even decades of operation. These include medical devices, aerospace, military, automotive, infrastructure and many more. Looking at the list above it should also be clear that many of these applications have implications for human safety. A broken cell phone is one thing, a malfunctioning aviation or automotive control system is quite another.

WEBINAR REPLAY: Challenges in analyzing High Performance clocks at 7nm and below process nodes

Verifying that a design meets timing specification, including clock tree skew, slew and jitter across process corners, while difficult, is a well understood process, with tools and methodologies available to support it. Evaluating if a chip has been designed to operate after 10 or 20 years of aging is a far more complex task, but an essential one. Frequently designers resort to guard banding to compensate for future aging effects. However, due to the nature of the processes involved in aging, simply adding timing margin may not be sufficient.

In fact, seemingly disconnected decisions about clock gating methods can have big effects on how aging manifests in older designs. Infinisim, a leading provider of clock tree analysis solutions, discusses the ins and outs of aging and how it can be minimized and simulated before tape out in a white paper titled “CMOS Transistor Aging and its impact on sub 10nm Clock Distribution”. The clock tree plays a critical role in aging and is a good place to start when looking to minimize aging effects.

The Infinisim white paper starts by covering the two major effects that cause transistor aging in devices below 10nm. They are Negative (or Positive) Bias Temperature Instability (NBTI/PBTI) and Hot Carrier Injection (HCI). NBTI and PBTI tend to affect transistors while they are at DC, with NMOS devices affected by high gate voltages and PMOS affected by low gate voltages. The result is that there can be asymmetrical aging effects, depending on where gate voltages are parked during clock gating, for example. Because aging on devices affects threshold voltages and slew rates, clock signals can experience shifts in duty cycles depending on clock gating design strategies.

HCI is influenced by switching events and operating currents, rather than static device state. The Infinisim paper describes the nuances of how circuit design can affect how aging will change the behavior of a design. The paper then goes on to talk about how predicted device aging effects can be used as inputs to clock tree analysis to see if timing will be affected as chips undergo aging effects. With Infinisim tools designers can look for aging issues and then apply changes to clock gating, such as holding a clock high versus low, etc. It is then possible to iterate and look to see if issues such as duty cycle distortion, clock skew, slew or insertion delay are going to be a problem.

Infinisim has a pioneering solution for clock tree analysis even when aging is not being looked at. It enables rapid turnaround of complete clock tree behavior to ensure design closure. Now, with the ability to factor in aging effects, Infinisim offers a unique ability to help ensure that mission critical SOCs will fulfill their life expectancy requirements. The full white paper makes interesting reading and can be found on the Infinisim website.

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WEBINAR: Challenges in analyzing High Performance clocks at 7nm and below process nodes