Cadence Dynamic Duo Upgrade Debuts

Cadence calls their hardware acceleration platforms, Palladium Z2 for fast pre-silicon hardware debug and Protium X2 for fast pre-silicon software validation, their Dynamic Duo. With good reason. Hardware acceleration is now fundamental to managing the complexity of verification and validation for large systems, hardware and software. What makes these platforms stand out in the market is raw capability (2X capacity, 1.5X performance over the earlier models) and also close interoperability. Hence, the Dynamic Duo. That interoperability proves to be very important in real-world applications.

Reinforcing the Strategy

The Cadence System & Verification Group strategy builds on the wider corporate strategy of excelling in computational software and enabling design excellence. The Cadence team meets this objective through a 3-layer solution. At the bottom, they lean on a wide range of compute hardware options, above that the fastest, most scalable verification engines they can build running on that hardware, and above that, a verification management tier to accelerate verification setup, debug and results gathering.

Palladium is their emulation engine, built on their own custom processor. The latest Palladium Z2 release is a redesign fabricated on a more advanced process. Protium X2 is also a redesign, built on the latest Xilinx UltraScale+ VU19P FPGA. Paul Cunningham, Sr. VP/GM of the System & Verification Group, tells me excelling in computational software means Cadence doesn’t compromise on individual engine throughput. For each verification objective, they’re using the best available hardware platform, which he sees as a parallel to the more general trend in fusion between hardware and software (such as we see in AI), using special purpose hardware to accelerate computation.

Interoperability

The Dynamic Duo name comes through the tight use-model correspondence between Palladium and Protium. There’s an important reason for that correspondence. Verifying or validating large systems, multi-billion gate SoCs together with software, maybe sitting in a larger in-circuit emulation (ICE) environment, can be quite iterative in practice. You want to regress a software stack on the hardware at fast as possible, so you run on Protium X2 (faster than Palladium in throughput). A hardware bug crops up. You switch over to Palladium Z2 for hardware debug (not quite as fast but better than Protium for hardware debug), find and fix the bug, then switch back to Protium to continue software regressions.

Making this switch back and forth as simple and as fast as possible can only be achieved through identical compile, identical testbench links, transactors, bridges, hardware, connectors. None of your carefully crafted setup has to change.

Optimizing ROI

Hardware acceleration platforms are more expensive than new copies of a software simulator, no surprise. You don’t want expensive hardware sitting idle during debug or chip projects because it can only run one job at a time. Both Palladium and Protium can operate as virtualizable resources in a data center. You can load up one giant job or many smaller jobs, which a dedicated hypervisor will pack as efficiently as possible onto the machine. Meaning you can run around-the clock SoC and sub-system verification jobs.

The rubber meets the road

All sounds good, who has signed up? AMD and NVIDIA have publicly endorsed both platforms and Arm has publicly endorsed Palladium Z2.

More generally on the mix between Palladium and Protium, Paul tells me that some customers use Protium almost exclusively. These design teams tend to be using a lot of pre-validated IP. Their verification leans to more emphasis on the software stack. Others are doing a lot of their own RTL design and require hardware debug access so lean more to Palladium. He added that a growing segment of Cadence’s hardware business last year came from customers buying a mix of both platforms. Reinforcing that customers are seeing significant value in the Dynamic Duo.

You can learn more HERE.

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