CEO Interview: Jason Xing of Empyrean Software

It’s been about seven years since Randy Smith last interviewed Jason Xing, the President/CEO of North America for Empyrean Software, so the timing felt good for a fresh update. I’ve been watching Empyrean at DAC for several years now, and have come away impressed with their growth and focus on some difficult IC design problems:

• GPU-powered SPICE circuit simulator (ALPS-GT)
• High capacity, parallel SPICE circuit simulator (ALPS)
• IC Layout Analysis and chip finishing (Skipper)
• Timing ECO (Empyrean XTop)

Q&A

How has Empyrean adapted to the pandemic, is work continuing but remotely?

Every year Empyrean has made significant investment in R&D which forms a big portion of its staffing. After the Pandemic broke out, we quickly enabled most employees to work from home by setting up remote server access and expanding online meeting capacities from Zoom and Webex. The pandemic limited employee mobility but saved on their commute time. Our customer engagement teams use this extra time to make deeper business planning, review case studies, and catch up on product technologies.

Has Empyrean been using Video technology to keep in contact with its employees and customers, or have you adopted any new apps to keep the business running and support customers?

Empyrean has used most major video technologies like Zoom, Webex, and XYLink. Also we use wechat for small scale and casual meetings as well.

With fewer trade shows and conferences happening in 2020, how will Empyrean connect with new customers?

Some of our target new customers were incubated in the past. During this pandemic, we just continue the business engagements through video technology communication and tool evaluations. We also try to reach new customers with online articles and webinars.

2019 just wrapped up, so what kind of progress did Empyrean make last year in the EDA industry?

In 2019, Empyrean successfully released a new product, the GPU powered, high performance, parallel SPICE simulator, ALPS-GT, which achieved over 10X performance speedup over competitors on large, post-layout simulation with high accuracy. This product has been adopted by several top-tier design houses and IP vendors.

Empyrean has also developed and perfected a design flow for flat-panel designs, which have been adopted major FPD IDMs.

What are the current semiconductor design challenges that your company is addressing in 2020?

We’re focused on the following four design challenges:

Analog design verification, including traditional analog design, structured memory design, and RF designs.

Difficult to debug, post-layout AMS designs at advanced nodes,

STA signoff is too pessimistic and cannot guard-band designs for very advanced design process and IOT designs,

Library characterization is too power and time-consuming for advanced design processes.

What kind of events will Empyrean be attending this year?

Empyrean will attend DAC, TSMC Symposium and OIP.

Which customers can you talk about from 2019 that were using Empyrean tools for IC design?

nVidia and Xilinx.

What would a successful 2020 look like for Empyrean?

Successfully roll out planned technology in our disruptive products and gain customer satisfaction for our products and support.

How do you compete with the solutions from big EDA companies?

Empyrean builds a competitive edge with  innovative or disruptive technologies to create products in a niche or void market place. Also, Empyrean tries to provide the best available customer support as well.

Did you see much competition for ALPS in the circuit simulation segment and how did you address it?

Yes. We did see competition. However, we saw that major competitors used massive RC reduction in order to gain simulation speed, which is not acceptable for post-layout simulation of designs with high accuracy at advanced nodes. Our ALPS/ALPS-GT circuit simulators excel in this type of long, accurate simulation and also our product team are still working hard to provide best innovations to achieve fast and accurate simulation for such designs.

Summary

I like the new products coming out of Empyrean for IC designers, and their customers include tier one semiconductor companies, all good signs. To take the next step, just contact Empyrean in Silicon Valley, China, Japan, Korea or Singapore. Empyrean also has a new webinar coming up. Even if you cannot attend on that day register and you will get a link to the replay:

WEBINAR: IP Integration Challenges of Complex SoC Platforms

Also read:

• Viewing the Largest IC Layout Files Quickly
• Automating Timing Arc Prediction for AMS IP using ML
• Speeding up Circuit Simulation using a GPU Approach
• The Changing Landscape for SPICE Circuit Simulators

More CEO Interviews:

Executive Interview: Howie Bernstein of HCL

CEO Interview: Adnan Hamid of Breker Systems

CEO Interview: Cristian Amitroaie of AMIQ EDA