Mentor at DVCON 2020!

Are you ready for the premier conference for functional design and verification of electronic systems?

Sponsored by Accellera Systems Initiative, DVCon is an independent, not-for-profit organization dedicated to creating design and verification standards required by systems, semiconductor, intellectual property (IP) and electronic design automation (EDA) companies.

This year at DVCon, you’ll find Mentor experts featured prominently throughout the conference program discussing the latest in Portable Stimulus, UVM, Formal, CDC, Low- Power Verification, High-Level Synthesis, and much more.

A full list of Mentor activities, can be found here.

SPONSORED LUNCHEON
Optimizing Time to Bug, Don’t Panic!!!
Thursday, March 5 | 11:45am – 12:45am | Sierra

Come join Tom Fitzpatrick, Strategic Verification Architect at Mentor, a Siemens Business, as he explores the myriad factors that contribute to verification complexity and how the changing landscape of electronics will expose new challenges in the continuing quest to find and eliminate bugs as early and effectively as possible.

FEATURED TUTORIAL
Application Optimized HW/SW Design & Verification of a Machine Learning SoC
Thursday, March 5 | 8:30am – 11:30am | Donner

This tutorial walks through the process of migrating an algorithm from generic software to a hardware implementation customized to the specific requirements of your system; making intelligent trade-offs between hardware and software along the way. It will explain the tools and techniques needed to go from “Software to Systems” and cover a broad range of solutions including simulation, emulation, prototyping, and High-Level Synthesis to design and verify SoCs and the software that runs on them.

FEATURED PANEL
Predicting the Verification Flow of the Future
Wednesday, March 4 | 1:30pm – 2:30pm | Oak/Fir

Moderator Jean-Marie Brunet from Mentor, a Siemens Business, will take a panel of verification experts on an exploration of what the verification environment of the future will look like. They will attempt to predict the longevity of simulation and formal verification and determine how far emulation will be able to extend through the entire verification flow. The role of standards will be addressed, as will when analog will have a place in digital functional verification.

SHORT WORKSHOPS
How HLS and SystemC is Delivering on its Promise of Design and Verification Productivity
Monday, March 2 | 3:30pm – 5:00pm | Oak

Mind the GAP(s): Closing and Creating GAPS between Design and Verification
Thursday, March 5 | 1:00pm – 2:30pm | Siskiyou

PAPER SESSIONS
Designing PSS Environment Integration for Maximum Reuse
Tuesday, March 3 | 9:00am – 10:30am | Fir

UVM – Stop Hitting Your Brother Coding Guidelines
Tuesday, March 3 | 3:00pm – 5:00pm | Oak

Multi-Level Replay of VIP Models in Isolation from Original Design Verification Environment to Enhance Protocol Analysis and Debug
Tuesday, March 3 | 3:00pm – 5:00pm | Fir

UPF 1.0, UPF 2.0, UPF 2.1, UPF 3.0, and Now UPF 3.1: The Big Q “Which is the Right Standard for My Design?”
Tuesday, March 3 | 3:00pm – 5:00pm | Monterey/Carmel

Did Power Management Break My CDC Logic? An Integrated Approach to Power Domain and Clock Domain Crossing Verification
Tuesday, March 3 | 3:00pm – 5:00pm | Monterey/Carmel

Systematic Methodology to Solve Reset Challenges in Automotive SoCs
Wednesday, March 4 | 3:00pm – 4:30pm | Monterey/Carmel

Scalable Reset Domain Crossing Verification Using Hierarchical Data Model
Wednesday, March 4 | 3:00pm – 4:30pm | Monterey/Carmel

SystemVerilog Constraints: Appreciating What You Forgot in Class to Get Better Results
Wednesday, March 4 | 3:00pm – 4:30pm | Oak

POSTER SESSIONS
Tuesday, March 3 | 10:30am – 12:00am | Gateway Foyer

4.3 – Covergate: Coverage Exposed

4.8 – How UPF 3.1 Reduces the Complexities of Reusing Power Aware Macros

4.11 – Are You Safe Yet? Safety Mechanism Insertion and Validation

4.14 – Deadlock Verification for Dummies – The Easy Way Using SVA and Formal

EXHIBIT FLOOR
You’ll find Mentor experts in booth #404 presenting daily theater sessions and running the latest Enterprise Verification Platform demos across Emulation, Low Power, Formal, Portable Stimulus, High-Level Synthesis, Verification IP, Debug, and more!

Mentor has pioneered technology to close the design and verification gap to improve productivity and quality of results. Catapult High-Level Synthesis for C-level verification and PowerPro for power analysis; Questa for simulation, low-power, VIP, CDC, Formal and support for UVM and Portable Stimulus; Veloce for hardware emulation and system of systems verification, unified with the Visualizer debug environment.