Full Solution for eMRAM Coming in 2020

It’s amazing to think that Apollo moon mission used computers that were based on magnetic core memories. Of course, CMOS memories superseded them rapidly. However, over the decades since, memory technologies have advanced significantly, in terms of density, power and new types of technologies, e.g NAND Flash. Ever since the 90’s magnetoresistive technology has been under investigation. Now Spin Torque Transfer Magnetic Random Access Memory (STT-MRAM) is becoming feasible and bringing with it many advantages over SRAM and/or NAND Flash. STT-MRAM fits in an interesting niche where it can be used for a variety of applications with big benefits.

In particular, it is very well suited for embedded memory applications. Embedded MRAM (eMRAM) has a much smaller cell size than SRAM, being comparable to NAND Flash. However, unlike NAND Flash it only requires an additional 2 or 3 mask layers, making it much easier to add to a CMOS die. Unlike NAND Flash it does not have endurance issues. This will be very important, especially to companies that have seen field issues with NAND Flash failures due to heavy write activity. STT-MRAM has a much faster write time that NAND Flash, making it a good choice for replacing last-level cache SRAM. The non-volatility opens up the ability to improve system architectures so that working memory does not need to be loaded at system start or wakeup.

The commercialization of eMRAM is progressing quickly. Mentor has just announced their partnership with Samsung and ARM to bring the full flow for developing products that use eMRAM. Samsung will offer eMRAM on its 28nm SOI process. ARM is developing the memory compilers, and Mentor will offer an IC test solution for it. Mentor’s Tessent software will offer BIST for the next generation ARM eMRAM compiler.

Because this is an entirely new technology it requires close collaboration between all three companies. They have already forged strong relationships from previous development activities. One of the big differences with eMRAM is that it is inherently probabilistic. This means specialized error correction should be used. Also, trimming is needed to reliably differentiate between a read 0 and 1. The test solution for eMRAM has to be developed with these key differences in mind. ARM and Mentor have stated that they are working to ensure that the complete flow offers the highest yield and quality.

According to Mentor the technology is still developing and each of the three companies is working together closely to fully understand all of the aspects that need to be considered to implement a comprehensive Memory BIST solution. A big part of the development process is using preliminary silicon to validate the flow and methodology. They expect to provide a solution to their key customers the second half of 2020.

A lot of work has gone into this technology. Just as LEDs, FinFETs and NAND Flash brought enormous changes to the systems they would be used in, eMRAM has the potential to bring about unforeseen changes as well. I always enjoy hearing about some technology that moves from being ‘under research’ to commercial rollout. More information about the Mentor Tessent announcement on eMRAM can be found on the Mentor website.