hip webinar automating integration workflow 800x100 (1)
WP_Term Object
    [term_id] => 157
    [name] => EDA
    [slug] => eda
    [term_group] => 0
    [term_taxonomy_id] => 157
    [taxonomy] => category
    [description] => Electronic Design Automation
    [parent] => 0
    [count] => 3900
    [filter] => raw
    [cat_ID] => 157
    [category_count] => 3900
    [category_description] => Electronic Design Automation
    [cat_name] => EDA
    [category_nicename] => eda
    [category_parent] => 0

TSMC ♥ Oasys

TSMC ♥ Oasys
by Paul McLellan on 01-31-2013 at 8:05 pm

 Oasys has joined the TSMC Soft-IP Alliance Program. This means that TSMC IP partners have access to a new RTL exploration tool to improve QoR and reduce the iterations needed for design closure. In modern process nodes, RTL engineers implementing complex IP cores for graphics, networking, and mobile computing are struggling with new QoR and time to market issues.

RealTime Explorer enables RTL engineers to have a physically aware, implementation accurate synthesis tool for top-level PPA and routing analysis without requiring them to be physical design experts. Without an accurate tool like RealTime Explorer, RTL designers either ignore physical design issues and their impact on timing and physical issues such as congestion. Or else they have to go through a complete iteration of physical design which can take days, even assuming that tools and physical design engineers are available to perform the work.

One feature that makes a big productivity difference is the logical-to-physical cross-probing capability that makes it easy to get at the root cause of timing and routing issues before even handing the design off for physical design. It is simple to go straight from the violation in the physical domain and connect straight back to the line(s) of RTL that originate the problem.

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