Keynote: On-Package Chiplet Innovations with UCIe

In the rapidly evolving landscape of semiconductor technology, the Universal Chiplet Interconnect Express (UCIe) emerges as a groundbreaking open standard designed to revolutionize on-package chiplet integrations. Presented by Dr. Debendra Das Sharma, Chair of the UCIe Consortium and Intel Senior Fellow, at the Chiplet Summit 2026, UCIe addresses the limitations of traditional monolithic SoC designs by enabling modular, high-performance chiplet architectures. As Moore’s Law slows, chiplets offer a path to overcome reticle size constraints, reduce development time, lower costs, and optimize yields through smaller dies and process-specific optimizations. UCIe positions System-in-Package as the new SoC, fostering an ecosystem where chiplets from diverse vendors can seamlessly interconnect, much like PCIe or USB at the board level.

The motivation for chiplets and UCIe stems from the need to scale innovation in an era where manufacturing processes lock certain IPs, and bespoke solutions demand flexibility. By mixing and matching dies with a standard interface, UCIe reduces portfolio costs, enables die reuse, and supports heterogeneous integrations across AI, HPC, cloud, edge, enterprise, 5G, automotive, and handheld segments. Founded in March 2022 and incorporated in June, the UCIe Consortium now boasts over 140 members, including industry giants like AMD, Arm, Intel, NVIDIA, Qualcomm, Samsung, and TSMC. It operates on guiding principles of openness, backward compatibility, optimized power-performance-cost metrics, and continuous innovation, drawing from decades of board-level standards experience.

UCIe’s evolution spans three generations of innovations, each building on the last for interoperability. UCIe 1.0, released in 2022, focuses on planar interconnects with a layered stack: physical layer for die-to-die I/O, adapter for reliable multi-protocol support (including PCIe, CXL, and streaming), and form factor definitions. It supports 2D (UCIe-S) for cost-effective longer distances and 2.5D (UCIe-A) for power-efficient high bandwidth density, enabling usages like I/O attachment, memory expansion, and accelerators. UCIe 1.1, from 2023, enhances automotive reliability with preventive monitoring and run-time testability via parity Flit injection, adds full-stack streaming protocol support, and optimizes costs for advanced packaging all while maintaining backward compatibility.

UCIe 2.0 introduces vertical stacking with UCIe-3D, leveraging hybrid bonding for bump pitches under 1µm, delivering areal connectivity that boosts bandwidth density dramatically. This generation emphasizes low power through simple circuits, SoC-frequency operations, and cluster-level repair, achieving performance rivaling monolithic dies. It includes comprehensive testability, manageability, and debug infrastructure, using sideband channels for remote access and a management fabric based on MCTP standards. UCIe 3.0, slated for 2025, doubles bandwidth to 48-64 GT/s, supports continuous transmission protocols for SoC-DSP connectivity, and adds power-saving features like runtime recalibration.

Key metrics underscore UCIe’s superiority. For UCIe-S (2D), bandwidth shoreline reaches 28-224 GB/s/mm (up to 1317 with 3.0), with power efficiency at 0.5-0.75 pJ/b. UCIe-A (2.5D) offers 278-370 GB/s/mm shoreline and 0.25-0.5 pJ/b, while UCIe-3D achieves up to 300,000 GB/s/mm² density and <0.01 pJ/b at 1µm pitches. Reliability targets near-zero FIT rates, with ESD protections scaling down. These KPIs ensure UCIe delivers high-bandwidth, low-latency, cost-effective interconnects across packages.

Demonstrations highlight UCIe’s maturity: The 2023 Synopsys-Intel interoperability test showed successful linkup and data traffic, while Ayar Labs’ 2025 OFC demo featured an 8 Tbps optical chiplet. Adoption is surging, with Synopsys trends indicating most HPC/AI designs are multi-die, projecting a $411B chiplet market by 2035 at 15.7% CAGR.

Looking ahead, UCIe enables rack/pod-level composability via optical retimers carrying CXL protocols, extending on-package innovations off-package. The consortium invites contributor and adopter memberships to drive future enhancements. In conclusion, UCIe is poised to democratize chiplet ecosystems, accelerating innovation and efficiency in computing. Its open, evolving framework ensures long-term investment protection, marking a pivotal shift in semiconductor design.

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