CEO Interview: Jason Xing of ICScape Inc.

I recently had the opportunity to interview Jason Xing, Ph.D., CEO and President of ICScape, Inc. Below is a subset of the nearly two hour long interview.

How did you first become involved in EDA?
My EDA career started in the mid-90s when I started working on my PhD thesis at the University of Illinois in Urbana-Champaign. My thesis topic was on parallel algorithms for standard cell based placement. After graduation in 1997, I joined Sun Labs doing research on new physical design methodologies using concurrent logical and physical design. At that time, physical synthesis was becoming a critical need for high performance VLSI designs.

How did you end up at ICScape? How do you feel about the evolution of your role with ICScape?
After several years of research at Sun Labs, in 2001 I joined Sun’s internal physical design development team to lead the geometrical database design and router development, where I met Dr. Steve Yang. We talked often on the physical design issues and EDA tool limitations. We decided to start a company to develop effective tools for physical design. In 2004, I quit Sun, and started working on setting up ICScape Inc. In the early years of ICScape, I was the CTO and VP of Engineering in charge of the product architecture and development. After the products, TimingExplorer™ and ClockExplorer™ were developed and achieved good market traction, the board of directors requested me to take on the role of CEO and run ICScape. I saw this as a great opportunity and a challenge. It has opened a new chapter in my career.

What are the specific design challenges your customers are facing?
For large SoC designs, it takes too long and there are too many iteration to close timing due the fact that timing sign off and implementation tools are using different timing engines, creating a major correlation issue. Timing closure typically involves up to hundreds of corners and modes, and requires setup, hold, max. transition, and max. capacitance violations to be addressed. In today’s designs, thousands of timing violations are found by the sign off STA (static timing analysis) engine. Fixing them using STA’s timing engine or with the users’ custom scripts means that the placement and routing constraints and requirements are not taken into account at all. This is the reason for too many iterations. On the other hand, it is difficult for current P&R tools to address timing closure because they can handle only a few modes and corners at a time. In addition, their lack of timing correlation with signoff STA is a major hurdle against closure.

What are your plans for DAC this year? What is your goal for DAC?
Continue to promote our SoC design closure products, which include our flagship product TimingExplorer. This tool solves placement and routing aware timing ECOs, and is capable of handling all multi-corner, multui-mode (MCMM) scenarios together. Since the introduction of the company and its products at DAC last year, some of our products have received a high level of interest from potential customers. We have closed several high profile accounts and are in active evaluation with other companies. We want to continue the momentum and increase the customer base.

How does your company help with your customers’ design challenges?
Timing closure is a major issue for customers. TimingExplorer fully addresses the two major limitations of current tools and methods: 1) lack of timing correlation between STA and P&R tools and 2) an inability to simultaneously handle all MCMM timing scenarios. This is done by directly mapping timing graphs from the sign-off STA engine on to the built-in timing engine and leveraging a built-in P&R engine, capable of simultaneously handling all MCMM timing scenarios to generate ECO directives for the sign-off STA as well as the user’s P&R engine.
The results are better and faster timing closure using typically 2-4 iterations and cutting ECO time by 50%.

What are the tool flows your customers are using?
Major P&R and timing signoff flow. P&R flow include ICC and SoC Encounter EDI. Timing signoff flow tools include PrimeTime and ETS.

ICScape is currently aiding customers in timing closure and in the creation of clock tree synthesisconstraints, what adjacent areas do you think might make sense for ICScape to enter in the future?
We could and would like to do more in chip finishing and low power physical design solutions including low power clock trees, and dynamic and leakage power reduction.

To visit with ICScape at DAC, click here.

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