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Xilinx
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FPGAs – The Possibilities are Endless – Almost

FPGAs – The Possibilities are Endless – Almost
by Luke Miller on 04-26-2013 at 8:00 pm
Categories: FPGA, Xilinx

Has your wife ever said “Your name, I’m not a computer”? Well maybe mine has. I know what you are thinking… This guy is married? Yup, I over achieved too. Have child #7 on the way Lord willing, so you probably guessed I don’t follow much of the world’s planning and such. Like you, no one in my house really understands what I do, nor cares … Read More

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FPGA + MATLAB = FATLAB

FPGA + MATLAB = FATLAB
by Luke Miller on 04-21-2013 at 7:00 pm
Categories: FPGA, Xilinx

Now Michael Bloomberg probably wouldn’t want FATLAB but let’s face it, to think like him you need a lot of education, alot. He may be banning 14nm because it will increase FPGAs densities and thus the consumer as well. Stay tuned. After some comments from my dear readers, one who said to watch it with respect to my harshness about… Read More

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FPGAS – The New Single Board Computers?

FPGAS – The New Single Board Computers?
by Luke Miller on 04-16-2013 at 10:00 pm
Categories: FPGA, Xilinx

I have always felt that FPGAs have been the red haired step child of Silicon Valley. Software weenies have hated them, they are mysterious and take too long to route. Even though they can be massively parallel and the most deterministic piece of silicon you can buy besides a million dollar ASIC, the GPU steals their glory, for now. … Read More

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Xilinx: Hide the RTL

Xilinx: Hide the RTL
by Paul McLellan on 04-16-2013 at 7:30 pm
Categories: FPGA, Xilinx

Tom Feist of Xilinx presented here at the GlobalPress Electronics Summit about their strategy to take design abstraction up another level. In the SoC world, we are still pretty much stuck at the RTL level and have moved to higher abstractions by using an IP strategy. But at least all IC designers are RTL-literate.


Xilinx, in the Vivado… Read More

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Ivo Bolsens’ Keynote on the All-Programmable SoC

Ivo Bolsens’ Keynote on the All-Programmable SoC
by Paul McLellan on 04-13-2013 at 8:00 pm
Categories: FPGA, Xilinx

Ivo Bolsens, the CTO of Xilinx, is giving the opening keynote at the Electronic Design Process Symposium (EDPS) in Monterey on Thursday and Friday this coming week. The title of his keynote is The All Programmable SoC – At the Heart of Next Generation Embedded Systems. He covers a lot of ground but the core of his presentation… Read More

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How to make ESL really work – see EDPS

How to make ESL really work – see EDPS
by John Swan on 04-12-2013 at 6:53 pm
Categories: FPGA, Xilinx

The Electronic Design Process Symposium (EDPS) is April 18 & 19 in Monterey. The workshop style Symposium is in its 20[SUP]th[/SUP] year. The first session is titled “ESL & Platforms”, which immediately follows the opening Keynote address by Ivo Bolsens, CTO of Xilinx.

In his keynote presentation Ivo will present how… Read More

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High Level Synthesis – It’s for Real

High Level Synthesis – It’s for Real
by Luke Miller on 04-11-2013 at 8:30 pm
Categories: FPGA, Xilinx

It was spring 2010 and I was asked to attend an HLS (High Level Synthesis) meeting. To be honest I cringed, after my bad relationship with Accel DSP and broken promises my heart was all walled up and needed counseling. But my management had a way of making me an offer I could not refuse, like keeping my job. So reluctantly I went. Does your… Read More

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A Non Deterministic Timing Problem

A Non Deterministic Timing Problem
by Luke Miller on 04-07-2013 at 2:00 pm
Categories: FPGA, Xilinx

When I was not messing around with FPGA Research and Development, or Algorithms, I was often called into the lab or field and presented this type of scenario… Most of the time, the fix was the same…

At least a few times a year, I’d get the call. Sometimes a panic in the voice, or sometimes defeat. And who wouldn’t be defeated? After… Read More

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3D Architectures for Semiconductor Integration and Packaging

3D Architectures for Semiconductor Integration and Packaging
by Paul McLellan on 12-10-2012 at 4:00 am
Categories: FPGA, Xilinx

There is obviously a lot going on in 3D IC these days. And I don’t mean at the micro level of FinFETs which is also a way of going vertical. I mean through-silicon-via (TSV) based approaches for either stacking die or putting them on an interposer. Increasingly the question is no longer if this technology will be viable (there… Read More

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Xilinx Programmable Packet Processor

Xilinx Programmable Packet Processor
by Paul McLellan on 10-17-2012 at 5:19 pm
Categories: FPGA, Xilinx

At the Linley conference last week I ran into Gordon Brebner of Xilinx. He and I go a long way back. We had adjacent offices in Edinburgh University Computer Science Department back when we were doing our PhDs and conspiring to network the department’s Vax into the university network over a two-week vacation. We managed to … Read More