Has your wife ever said “Your name, I’m not a computer”? Well maybe mine has. I know what you are thinking… This guy is married? Yup, I over achieved too. Have child #7 on the way Lord willing, so you probably guessed I don’t follow much of the world’s planning and such. Like you, no one in my house really understands what I do, nor cares much. Hey they are like middle management; get ready for your yearly review where acronyms’ are king, in my last review I was told I was not visible enough, so I guess I need to eat more. OK I need to stop. While humans have what would seem like infinite possibilities, and women are multithreaded and operate in a non-binary way, I look to the possibilities of the finite, non-personal FPGA for some amazement. My bumper sticker says “I break for HLS” (I stole that from my Xilinx Buddy)
Every time I test a new bit image on a new device and the FPGA passes the smoke test; done light is on and the math working, I think wow; I can’t believe this is working. Now, it is not because I’m that bad of a designer, I hide that well. I’m just in awe of all the things that have to work just to make my little algorithm crank away. Don’t get me wrong, it is not like watching a child being born, or even a seed popping thru the soil in my garden but the sheer magnitude of all the collective efforts around the world to get a FPGA on a board that works is simply amazing. From the Fab lines, to node characterization, IO design, Hard IP’s, 3[SUP]rd[/SUP] party tools to aid the layout, DRCs, parasitic modeling, place and route 10 times, I could keep going. The configuration scheme alone I’m sure is years’ worth of work. Inside of that wonder square of gates is billions of transistors, and you know what? They work! And not only that, they work for a long time, they are reliable. Did I forget to mention all the high speed, 20+ layer board design, the micro switching power supplies? I would have to say the demo board that I program, easily must of had 1000’s of paws helping out so I could make a design a reality. Now I know I missed a whole bunch in there so don’t get nervous, I know you helped too and if you’re dead wood you at least faked it, by the way, you are fooling no one, can you say sequester.
The largest Virtex-7 has a configuration bit stream of 293,892,224 bits. That’s a lot. Many, many possibilities. Now don’t get technical on me, let’s just say it’s the full 293,892,224 bits, and that could be 2^293,892,224 different designs. I wonder how long it would take to find my bit stream match for a beamformer design. That is a neat thought. Too bad it would take a billion years to find out but the idea is you design for expects not the function. I have always thought of the FPGA as a player piano. The bit stream is the music roll and we make the music. Now that we have bounded the FPGA’s possibilities and we see they are finite, but huge, does anyone know the maximum possibilities for a CPU? It is not infinite, can’t be, assume fixed clock speed. That question brings up two more thoughts, which are there is no such thing as random and infinite. Yes in theory they exist like helpful people at a help desk but you cannot find them in practice. Roll some dice, they obeyed physics, sum up all the matter in the universe divide by Planck mass and that’s all the smallest parts possible, not infinite. Mind boggling isn’t it? OK go program an FPGA.
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