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180nm still a big deal

180nm still a big deal
by Don Dingee on 05-07-2014 at 3:00 pm

When I was reading the recent Daniel Payne article “Designing Change Into Semiconductor Techonomics” with commentary on a recent presentation from Aart de Geus of Synopsys, one chart jumped out at me: the most popular process node for new design starts today is 180nm.

Upon mentioning that to a few of my IoT counterparts, they quickly… Read More


Intel is Still Missing Mobile!

Intel is Still Missing Mobile!
by Daniel Nenni on 05-07-2014 at 9:00 am

Paul McLellan was on assignment in Hong Kong last week so I attended the Linley Mobile Conference and was not surprised Intel did not present. During the networking sessions I asked more than a dozen people why and the answers were pretty focused on “Intel still does not play well with others” and “Intel’s current mobile offerings… Read More


FD-SOI : SMIC or…Who else?

FD-SOI : SMIC or…Who else?
by Eric Esteve on 05-01-2014 at 9:12 am

In fact, as of today, nobody can refer to an official statement made by any STM executive about name of the foundry able to process FD-SOI wafers in 28nm. We just know that the agreement is about to (or has been) signed… But we may speculate, and try to use our rational thinking. For example, the Semiwiki readers had the opportunity to… Read More


FD-SOI Not Just For France Any More, China Signs On?

FD-SOI Not Just For France Any More, China Signs On?
by Paul McLellan on 04-30-2014 at 9:07 pm

The COO of ST Microelectronics, Jean-Marc Chery announced that they have signed a new foundry agreement for FD-SOI. What he actually said doesn’t reveal who the foundry in question is:“We have just signed a strategic agreement with a top-tier foundry for 28nm FD-SOI technology. This agreement expands the ecosystem, assuresRead More


Tanner EDA Helps Customer Productivity Engineering Increase Efficiency and Lower Cost with No Compromise in Performance

Tanner EDA Helps Customer Productivity Engineering Increase Efficiency and Lower Cost with No Compromise in Performance
by Daniel Nenni on 04-29-2014 at 10:00 am

Tanner EDA is making waves at their customer’s sites as the mixed-signal design suite from Tanner EDA, Incentia Design Systems, Inc. and Aldec, Inc. helps ASIC Design House lower cost and increase efficiency with no compromise in performance. In today’s ‘always on’, Internet of Things connected world, the demand for high-performance,… Read More


FD-SOI Better Than FinFET?

FD-SOI Better Than FinFET?
by Paul McLellan on 04-27-2014 at 9:16 am

As I said earlier in the month, I was going to be talking about FD-SOI at the Electronic Design Process Symposium (EDPS) in Monterey. I am not especially an expert on FD-SOI but I know enough to be dangerous and given that we were already talking about FinFET and 3D/2.5D chips, it fitted in nicely.

The 10,000 foot view is that FD-SOI has… Read More


On-chip Firewall

On-chip Firewall
by Paul McLellan on 04-22-2014 at 8:00 am

We have had the Snowden revelations that the NSA has gone rogue, Target lost a zillion credit cards, the Heartbleed bug meaning that main security protocol of the internet had been coded up wrong for a couple of years, theft of records from RSA and more. One result is that people do not completely trust a security system that depends… Read More


NVM central to multi-layer trust in cloud

NVM central to multi-layer trust in cloud
by Don Dingee on 04-21-2014 at 4:00 pm

Pop quiz: Name one of the hottest applications for non-volatile memory – A) processor and code configuration; B) RFID tags; C) secure encryption keys; D) all the above. The answer is D, but not in the way you may be thinking; a new approach is using all these ideas at once, combined in SoC designs targeting advanced security … Read More


Does Processor IP still get the Lion’s share in 2013?

Does Processor IP still get the Lion’s share in 2013?
by Eric Esteve on 04-17-2014 at 1:00 pm

I think that the answer is pretty obvious, but the interesting point is to figure out which processor type, and which part of revenues, up-front license or royalties? One of my customers, let’s call him Mr. X, ask me to clarify this point. Mr. X has bought the excellent report from Gartner “Market Share: Semiconductor Design Intellectual… Read More


GSA 3DIC

GSA 3DIC
by Paul McLellan on 04-10-2014 at 6:27 pm

At the GSA Silicon Summit this afternoon there was a discussion of 3D IC and 2.5D IC. The session was moderated by Javier DeLaCruz of eSilicon and the panelists were:

  • Calvin Cheung of ASE (an OSAT)
  • Gil Lvey of OptimalTest (a test house)
  • Bob Patti of Tezzaron (semiconductor company specializing in TSV-based designs)
  • Riko Radojcic
Read More