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Webinar: Getting to Formal Coverage

Webinar: Getting to Formal Coverage
by Bernard Murphy on 04-20-2017 at 10:00 am

Facing rapidly growing challenges in getting to respectable coverage, designers have been turning more and more to formal verification, not just to plug gaps but increasingly to take over verification of significant components of the testplan. Which is great, but at the end of the day any approach to verification must be measured… Read More


When Will we Replace the 3.5 mm Jack in Modern Phones?

When Will we Replace the 3.5 mm Jack in Modern Phones?
by Eric Esteve on 04-05-2017 at 7:00 am

You have certainly experienced that modern mobile phones are used for more than phone calls and do not have room for multiple connectors. A new approach for audio connectivity is needed, allowing product designers to retire the 3.5mm jack. Considering the USB audio protocol to replace the analog audio solutions, typically using… Read More


SNUG and Robots

SNUG and Robots
by Bernard Murphy on 03-31-2017 at 7:00 am

I got an invite to the SNUG (Synopsys User Group meeting) keynotes this year. I could only make it to the second keynote but what a treat that was. The speaker was Dr. Peter Stone, professor and chair of CS at UT Austin. He also chaired the inaugural panel for the Stanford 100-year study on AI. This is a guy who knows more about AI than most… Read More


SNUG 2017 Keynote: Aart de Geus on EDA Fusion!

SNUG 2017 Keynote: Aart de Geus on EDA Fusion!
by Daniel Nenni on 03-30-2017 at 7:00 am

I spoke with Aart before his SNUG keynote and found him to be very relaxed and upbeat about EDA and our future prospects which reminded me of my first ever (cringe-worthy) blog, “EDA is Dead”. Now, eight years later, we have what Aart calls “EDA Fusion” to thank for the reemergence of EDA as a semiconductor superpower, absolutely.… Read More


A Formal Feast

A Formal Feast
by Bernard Murphy on 03-29-2017 at 7:00 am

It’s not easy having to deliver one of the last tutorials on the last day of a conference. Synopsys drew that short straw for their tutorial on formal methodologies at DVCon this year. Despite that they delivered an impressive performance, keeping the attention of 60 attendees who said afterwards it was excellent on technical content,… Read More


Virtual Modeling Drives Auto Systems TTM

Virtual Modeling Drives Auto Systems TTM
by Bernard Murphy on 03-27-2017 at 7:00 am

The electronics market for automotive applications is distinguished by multiple factors. This is a very fast growing market – electronics now account for 40% of a car’s cost, up from 20% just 10 years ago. New technologies are gaining acceptance, for greener and safer operation and for a more satisfying consumer experience. Platforms… Read More


Recipes for Low Power Verification

Recipes for Low Power Verification
by Bernard Murphy on 03-20-2017 at 7:00 am

Synopsys hosted a tutorial on verification for low power design at DVCon this year, including speakers from Samsung, Broadcom, Intel and Synopsys. Verification for low power is a complex and many-faceted topic so this was a very useful update. There is a vast abundance of information in the slides which I can’t hope to summarize… Read More


Driver Assistance and Autonomous? Need ASIL D Ready Certified CPU!

Driver Assistance and Autonomous? Need ASIL D Ready Certified CPU!
by Eric Esteve on 03-13-2017 at 12:00 pm

The automotive segment is moving from a kind of niche, filled with commodities and highly specialized low complexity IC, to an innovative and very dynamic segment attracting most of the big players, from Qualcomm to Nvidia or Intel. These chip makers are targeting automotive as they need to find new growth areas, and they have quicklyRead More


Synopsys and PhoeniX Demo Photonic IC Flow Using AIM PDK at OFC

Synopsys and PhoeniX Demo Photonic IC Flow Using AIM PDK at OFC
by Mitch Heins on 03-08-2017 at 12:00 pm


Synopsys has long been known for its leading position in the digital logic synthesis world. More recently however, the company started delving into the world of photonic integrated circuit (PIC) design. Synopsys started down this path from the system level with a 2010 acquisition of Optical Research Associates and their CODE… Read More


Using HSPICE StatEye to Tackle DDR4 Rail Jitter

Using HSPICE StatEye to Tackle DDR4 Rail Jitter
by Tom Simon on 02-15-2017 at 12:00 pm

The world is a risky place, according to Scott Wedge, Principal R&D Engineer at Synopsys, who presented at the Synopsys HSPICE SIG on Feb 2[SUP]nd[/SUP] in Santa Clara. Indeed, the world circuit designers face can be uncertain. Dealing with risk and departure from ideal was a main theme in the fascinating talks at this dinner… Read More